SLUSFQ1A December   2024  – December 2024 BQ41Z90

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions:
  6. 5 Pin Equivalent Diagrams
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Supply Current
    6. 6.6  Power Selector
    7. 6.7  Current Wake Detector
    8. 6.8  General Purpose Input-Outputs
    9. 6.9  Aux REGOUT LDO
    10. 6.10 LD Pin
    11. 6.11 Shelf Timer
    12. 6.12 Cell Balancing
    13. 6.13 Comparator-Based Detections (SCOMP)
    14. 6.14 SCOMP Timing Requirements
    15. 6.15 SCD Comparator
    16. 6.16 High-side NFET Drivers (CHG and DSG and PCHG and PDSG)
    17. 6.17 FUSE Pin
    18. 6.18 Flash Memory
    19. 6.19 Interface I/O
    20. 6.20 I2C Interface Timing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Functional Modes
        1. 7.3.1.1 Analog Front End (AFE)
        2. 7.3.1.2 Power Management
          1. 7.3.1.2.1 Power Mode Block Configuration
          2. 7.3.1.2.2 Power Supply Control
            1. 7.3.1.2.2.1 HIBERNATE Mode
            2. 7.3.1.2.2.2 SHUTDOWN Mode
            3. 7.3.1.2.2.3 SHELF Mode
            4. 7.3.1.2.2.4 Wake Functionality
          3. 7.3.1.2.3 Power Management Unit
            1. 7.3.1.2.3.1 PMU Overview
          4. 7.3.1.2.4 Thermal Shutdown
          5. 7.3.1.2.5 Low Drop Out Regulators (LDOs)
            1. 7.3.1.2.5.1 REG18
            2. 7.3.1.2.5.2 REG135
            3. 7.3.1.2.5.3 REGIO
            4. 7.3.1.2.5.4 REGOUT
        3. 7.3.1.3 Reset Management
          1. 7.3.1.3.1 RST_SD Pin Operation
          2. 7.3.1.3.2 AFE Watchdog
        4. 7.3.1.4 Diagnostics Features
        5. 7.3.1.5 Internal Oscillators
          1. 7.3.1.5.1 Low Frequency Oscillator (LFO)
          2. 7.3.1.5.2 High Frequency Oscillator (HFO)
          3. 7.3.1.5.3 Low Power Oscillator (LPO)
      2. 7.3.2 Temperature Measurement
        1. 7.3.2.1 External Temperature Measurement Support
        2. 7.3.2.2 Internal Temperature Sensor
      3. 7.3.3 Random Cell Connection Support
        1. 7.3.3.1 Usage of VC Pins for Cells Versus Interconnect
        2. 7.3.3.2 Unused Pins
      4. 7.3.4 Cell Balancing Support
        1. 7.3.4.1 Open Wire Detection
      5. 7.3.5 Protection and Charge Control Outputs
        1. 7.3.5.1 High-Side NFET Drivers
        2. 7.3.5.2 PRECHARGE and PREDISCHARGE Modes
        3. 7.3.5.3 FET Configuration
        4. 7.3.5.4 CFETOFF, DFETOFF Pin Functionality
        5. 7.3.5.5 DDSG and DCHG Pin Operation
        6. 7.3.5.6 Hardware Fault Detection (SCOMP and SCD)
        7. 7.3.5.7 FET UVLO Protection
        8. 7.3.5.8 Fuse Drive
      6. 7.3.6 Load Detect Functionality
      7. 7.3.7 MCU Peripherals
        1. 7.3.7.1 General Purpose and Special Function I/O
          1. 7.3.7.1.1 Low Voltage RAx I/O
          2. 7.3.7.1.2 Low Voltage RCx I/O
          3. 7.3.7.1.3 Constant Current Sink I/O
        2. 7.3.7.2 Communication Interfaces
          1. 7.3.7.2.1 I2C Interface
          2. 7.3.7.2.2 SMBus Interface
        3. 7.3.7.3 Authentication Support
          1. 7.3.7.3.1 ECC Authentication
          2. 7.3.7.3.2 SHA-1 Support
          3. 7.3.7.3.3 SHA-2 Support
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
  10. 9 Power Supply Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PVP|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3.2 Unused Pins

Some device pins may not be needed in a particular application. The manner in which each should be terminated in this case is described below.

Table 7-3 Terminating Unused Pins
Pin Name Recommendation
1–16, 64 VC0–VC16 Cell inputs 1, 2, and 16 should always be connected to actual cells, with cells connected between VC1 and VC0, VC2 and VC1, and VC16 and VC15. VC0 should be connected through a resistor and capacitor on the pcb to pin 49 (VSS). Pins related to unused cells (which may be cell 3–cell 15, pins 1–13) can be connected to the cell stack to measure interconnect resistance or provide a Kelvin-connection to actual cells, in which case they should include a series resistor and parallel capacitor, in similar fashion to pins connected to actual cells (see Section 7.3.3.1). Another option is to short unused VC pins directly to an adjacent VC pin. All VC pins should be connected to either an adjacent VC pin, an actual cell (through R and C) or stack interconnect resistance (through R and C).
17, 19 SRP, SRN If not used, these pins should be connected to pin 49 (VSS).
18, 33, 45, 46 NC These pins are not connected to silicon. They can be left floating or connected to an adjacent pin or connected to VSS.
20-23, 26-29, 34-44, 47-48 RADCx (0...8, except for RAD4) RAx, RCx, If not used, these pins (except for RADC4 _Wake) can be left floating or connected to pin 49 (VSS). Any of these pins (except for RADC4 _Wake) may be configured with the internal weak pulldown resistance enabled during operation, although this is not necessary.
24 RADC-Wake If the device is intended to enter SHUTDOWN mode, this pin should be left floating. If SHUTDOWN mode will not be used in the application,this pin can be left floating or connected to pin 17 (VSS).
25 RST_SD If not used, this pin should be connected to pin 49 (VSS).
52 REGOUT If not used, these pins can be left floating or connected to pin 49 (VSS).
53 REGIN If not used, this pin should be connected to pin 49 (VSS).
54 BREG If this pin is not used and pin 53 (REGIN) is also not used, both pins should be connected to pin 49 (VSS). If this pin is not used but pin 53 is used (such as driven from an external source), then this pin should be connected to pin 53 (REGIN).
51 FUSE If not used, this pin can be left floating or connected to pin 49 (VSS).
57 PDSG If not used, this pin should be left floating.
60 PCHG If not used, this pin should be left floating.
55 LD If the DSG driver will not be used, this pin can be connected through a series resistor to the PACK+ connector, or can be connected to pin 49 (VSS).
58 DSG If not used, this pin should be left floating.
61 CHG If not used, this pin should be left floating.
62 CP If not used, this pin should be connected to pin 63 (BAT).
Note: If the charge pump is enabled with CP1 connected to BAT, the device will consume an additional ≈200µA.