SLUSFQ1A December   2024  – December 2024 BQ41Z90

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions:
  6. 5 Pin Equivalent Diagrams
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Supply Current
    6. 6.6  Power Selector
    7. 6.7  Current Wake Detector
    8. 6.8  General Purpose Input-Outputs
    9. 6.9  Aux REGOUT LDO
    10. 6.10 LD Pin
    11. 6.11 Shelf Timer
    12. 6.12 Cell Balancing
    13. 6.13 Comparator-Based Detections (SCOMP)
    14. 6.14 SCOMP Timing Requirements
    15. 6.15 SCD Comparator
    16. 6.16 High-side NFET Drivers (CHG and DSG and PCHG and PDSG)
    17. 6.17 FUSE Pin
    18. 6.18 Flash Memory
    19. 6.19 Interface I/O
    20. 6.20 I2C Interface Timing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Functional Modes
        1. 7.3.1.1 Analog Front End (AFE)
        2. 7.3.1.2 Power Management
          1. 7.3.1.2.1 Power Mode Block Configuration
          2. 7.3.1.2.2 Power Supply Control
            1. 7.3.1.2.2.1 HIBERNATE Mode
            2. 7.3.1.2.2.2 SHUTDOWN Mode
            3. 7.3.1.2.2.3 SHELF Mode
            4. 7.3.1.2.2.4 Wake Functionality
          3. 7.3.1.2.3 Power Management Unit
            1. 7.3.1.2.3.1 PMU Overview
          4. 7.3.1.2.4 Thermal Shutdown
          5. 7.3.1.2.5 Low Drop Out Regulators (LDOs)
            1. 7.3.1.2.5.1 REG18
            2. 7.3.1.2.5.2 REG135
            3. 7.3.1.2.5.3 REGIO
            4. 7.3.1.2.5.4 REGOUT
        3. 7.3.1.3 Reset Management
          1. 7.3.1.3.1 RST_SD Pin Operation
          2. 7.3.1.3.2 AFE Watchdog
        4. 7.3.1.4 Diagnostics Features
        5. 7.3.1.5 Internal Oscillators
          1. 7.3.1.5.1 Low Frequency Oscillator (LFO)
          2. 7.3.1.5.2 High Frequency Oscillator (HFO)
          3. 7.3.1.5.3 Low Power Oscillator (LPO)
      2. 7.3.2 Temperature Measurement
        1. 7.3.2.1 External Temperature Measurement Support
        2. 7.3.2.2 Internal Temperature Sensor
      3. 7.3.3 Random Cell Connection Support
        1. 7.3.3.1 Usage of VC Pins for Cells Versus Interconnect
        2. 7.3.3.2 Unused Pins
      4. 7.3.4 Cell Balancing Support
        1. 7.3.4.1 Open Wire Detection
      5. 7.3.5 Protection and Charge Control Outputs
        1. 7.3.5.1 High-Side NFET Drivers
        2. 7.3.5.2 PRECHARGE and PREDISCHARGE Modes
        3. 7.3.5.3 FET Configuration
        4. 7.3.5.4 CFETOFF, DFETOFF Pin Functionality
        5. 7.3.5.5 DDSG and DCHG Pin Operation
        6. 7.3.5.6 Hardware Fault Detection (SCOMP and SCD)
        7. 7.3.5.7 FET UVLO Protection
        8. 7.3.5.8 Fuse Drive
      6. 7.3.6 Load Detect Functionality
      7. 7.3.7 MCU Peripherals
        1. 7.3.7.1 General Purpose and Special Function I/O
          1. 7.3.7.1.1 Low Voltage RAx I/O
          2. 7.3.7.1.2 Low Voltage RCx I/O
          3. 7.3.7.1.3 Constant Current Sink I/O
        2. 7.3.7.2 Communication Interfaces
          1. 7.3.7.2.1 I2C Interface
          2. 7.3.7.2.2 SMBus Interface
        3. 7.3.7.3 Authentication Support
          1. 7.3.7.3.1 ECC Authentication
          2. 7.3.7.3.2 SHA-1 Support
          3. 7.3.7.3.3 SHA-2 Support
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
  10. 9 Power Supply Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PVP|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.20 I2C Interface Timing

Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 105°C and VBAT = 5 V to 80 V (unless otherwise noted)
PARAMETERTEST CONDITIONSMINNOMMAXUNIT
I2C 100 kHz
fSCL Clock Frequency100kHz
tHD:STASTART Condition Hold Time4µs
tLOW LowPeriod of SCL Clock4.7µs
tHIGHHighPeriod of SCL Clock4µs
tSU:STASetup Time for repeated START4.7µs
tHD:DAT Data In Hold Time0µs
tSU:DAT Data in Setup Time250ns
Data out Setup Time250ns
tr(2)SDA and SCL Rise Time30% to 70% of VREGIO1000ns
tF (2)SDA and SCL Fall Time30% to 70% of VREGIO300ns
tSU:STO STOP Condition Setup Time4µs
tBUF Bus Free Time between STOP and START4.7µs
tVD:DAT(1)(3)(4)Data Valid Time3.45µs
tVD:ACK(1)(3)(4)Data Valid Acknowledge Time3.45µs
tBUSLOWMax SCL/SDA Low (BUSLOW) Signal Detect Time by deviceBUSLOWCNT = 0x10.5s
tBUSLOWMax SCL/SDA Low (BUSLOW) Signal Detect Time by deviceBUSLOWCNT = 0x21s
tBUSLOWMax SCL/SDA Low (BUSLOW) Signal Detect Time by deviceBUSLOWCNT = 0x42s
tBUSLOWMax SCL/SDA Low (BUSLOW) Signal Detect Time by deviceBUSLOWCNT = 0x73.5s
CDCapacitive load for each bus line400pF
I2C 400 kHz
fSCL Clock Frequency400kHz
tHD:STA START Condition Hold Time0.6µs
tLOW LowPeriod of SCL Clock1.3µs
tHIGH HighPeriod of SCL Clock0.6µs
tSU:STASetup Time for repeated START0.6µs
tHD:DAT Data In Hold Time0µs
tSU:DAT Data in Setup Time100ns
Data out Setup Time100ns
tr (2)SDA and SCL Rise Time30% to 70% of VREGIO20300ns
tF (2)SDA and SCL Fall Time30% to 70% of VREGIO20 * (VREGIO/5.5)300ns
tSU:STOSTOP Condition Setup Time0.6µs
tBUF Bus Free Time between STOP and START1.3µs
tVD:DAT(1)(2)(3)Data Valid Time0.9µs
tVD:ACK(1)(2)(3)Data Valid Acknowledge Time0.9µs
tBUSLOWMax SCL/SDA Low (BUSLOW) Signal Detect Time by deviceBUSLOWCNT = 0x10.5s
BUSLOWCNT = 0x21s
BUSLOWCNT = 0x42s
BUSLOWCNT = 0x73.5s
CDCapacitive load for each bus line400pF
I2C 1 MHz
fSCL Clock Frequency1000kHz
tHD:STA START Condition Hold Time0.26µs
tLOW LowPeriod of SCL Clock0.5µs
tHIGH HighPeriod of SCL Clock0.26µs
tSU:STASetup Time for repeated START0.26µs
tHD:DAT Data In Hold Time0µs
tSU:DAT Data in Setup Time50ns
Data out Setup Time50ns
tr (2)SDA and SCL Rise Time30% to 70% of VREGIO120ns
tF (2)SDA and SCL Fall Time30% to 70% of VREGIO20 * (VREGIO/5.5)120ns
tSU:STOSTOP Condition Setup Time0.26µs
tBUF Bus Free Time between STOP and START0.5µs
tVD:DAT(1)(2)(3)Data Valid Time0.45µs
tVD:ACK(1)(2)(3)Data Valid Acknowledge Time0.45µs
tBUSLOWMax SCL/SDA Low (BUSLOW) Signal Detect Time by deviceBUSLOWCNT = 0x10.5s
BUSLOWCNT = 0x21s
BUSLOWCNT = 0x42s
BUSLOWCNT = 0x73.5s
CDCapacitive load for each bus line100pF
(1) This maximum is only met if the device does not stretch the LOW period (tLOW) of the SCL signal.
(2) VREGIO can be 1.8V or 3.3V depending on OTP selection.
(3) tVD;DAT = time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
(4) tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).