SLUSFQ1A December   2024  – December 2024 BQ41Z90

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions:
  6. 5 Pin Equivalent Diagrams
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Supply Current
    6. 6.6  Power Selector
    7. 6.7  Current Wake Detector
    8. 6.8  General Purpose Input-Outputs
    9. 6.9  Aux REGOUT LDO
    10. 6.10 LD Pin
    11. 6.11 Shelf Timer
    12. 6.12 Cell Balancing
    13. 6.13 Comparator-Based Detections (SCOMP)
    14. 6.14 SCOMP Timing Requirements
    15. 6.15 SCD Comparator
    16. 6.16 High-side NFET Drivers (CHG and DSG and PCHG and PDSG)
    17. 6.17 FUSE Pin
    18. 6.18 Flash Memory
    19. 6.19 Interface I/O
    20. 6.20 I2C Interface Timing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Functional Modes
        1. 7.3.1.1 Analog Front End (AFE)
        2. 7.3.1.2 Power Management
          1. 7.3.1.2.1 Power Mode Block Configuration
          2. 7.3.1.2.2 Power Supply Control
            1. 7.3.1.2.2.1 HIBERNATE Mode
            2. 7.3.1.2.2.2 SHUTDOWN Mode
            3. 7.3.1.2.2.3 SHELF Mode
            4. 7.3.1.2.2.4 Wake Functionality
          3. 7.3.1.2.3 Power Management Unit
            1. 7.3.1.2.3.1 PMU Overview
          4. 7.3.1.2.4 Thermal Shutdown
          5. 7.3.1.2.5 Low Drop Out Regulators (LDOs)
            1. 7.3.1.2.5.1 REG18
            2. 7.3.1.2.5.2 REG135
            3. 7.3.1.2.5.3 REGIO
            4. 7.3.1.2.5.4 REGOUT
        3. 7.3.1.3 Reset Management
          1. 7.3.1.3.1 RST_SD Pin Operation
          2. 7.3.1.3.2 AFE Watchdog
        4. 7.3.1.4 Diagnostics Features
        5. 7.3.1.5 Internal Oscillators
          1. 7.3.1.5.1 Low Frequency Oscillator (LFO)
          2. 7.3.1.5.2 High Frequency Oscillator (HFO)
          3. 7.3.1.5.3 Low Power Oscillator (LPO)
      2. 7.3.2 Temperature Measurement
        1. 7.3.2.1 External Temperature Measurement Support
        2. 7.3.2.2 Internal Temperature Sensor
      3. 7.3.3 Random Cell Connection Support
        1. 7.3.3.1 Usage of VC Pins for Cells Versus Interconnect
        2. 7.3.3.2 Unused Pins
      4. 7.3.4 Cell Balancing Support
        1. 7.3.4.1 Open Wire Detection
      5. 7.3.5 Protection and Charge Control Outputs
        1. 7.3.5.1 High-Side NFET Drivers
        2. 7.3.5.2 PRECHARGE and PREDISCHARGE Modes
        3. 7.3.5.3 FET Configuration
        4. 7.3.5.4 CFETOFF, DFETOFF Pin Functionality
        5. 7.3.5.5 DDSG and DCHG Pin Operation
        6. 7.3.5.6 Hardware Fault Detection (SCOMP and SCD)
        7. 7.3.5.7 FET UVLO Protection
        8. 7.3.5.8 Fuse Drive
      6. 7.3.6 Load Detect Functionality
      7. 7.3.7 MCU Peripherals
        1. 7.3.7.1 General Purpose and Special Function I/O
          1. 7.3.7.1.1 Low Voltage RAx I/O
          2. 7.3.7.1.2 Low Voltage RCx I/O
          3. 7.3.7.1.3 Constant Current Sink I/O
        2. 7.3.7.2 Communication Interfaces
          1. 7.3.7.2.1 I2C Interface
          2. 7.3.7.2.2 SMBus Interface
        3. 7.3.7.3 Authentication Support
          1. 7.3.7.3.1 ECC Authentication
          2. 7.3.7.3.2 SHA-1 Support
          3. 7.3.7.3.3 SHA-2 Support
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
  10. 9 Power Supply Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PVP|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions:

BQ41Z90 Pin Diagram Figure 4-1 Pin Diagram
Table 4-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
VC151AISense voltage input pin for the fifteenth cell from the bottom of the stack, balance current input for the fifteenth cell from the bottom of the stack, and return balance current for the sixteenth cell from the bottom of the stack
VC142AISense voltage input pin for the fourteenth cell from the bottom of the stack, balance current input for the fourteenth cell from the bottom of the stack, and return balance current for the fifteenth cell from the bottom of the stack
VC133AISense voltage input pin for the thirteenth cell from the bottom of the stack, balance current input for the thirteenth cell from the bottom of the stack, and return balance current for the fourteenth cell from the bottom of the stack
VC124AISense voltage input pin for the twelveth cell from the bottom of the stack, balance current input for the twelveth cell from the bottom of the stack, and return balance current for the thirteenth cell from the bottom of the stack
VC115AISense voltage input pin for the eleventh cell from the bottom of the stack, balance current input for the eleventh cell from the bottom of the stack, and return balance current for the twelfth cell from the bottom of the stack
VC106AISense voltage input pin for the tenth cell from the bottom of the stack, balance current input for the tenth cell from the bottom of the stack, and return balance current for the eleventh cell from the bottom of the stack
VC97AISense voltage input pin for the ninth cell from the bottom of the stack, balance current input for the ninth cell from the bottom of the stack, and return balance current for the tenth cell from the bottom of the stack
VC88AISense voltage input pin for the eighth cell from the bottom of the stack, balance current input for the eighth cell from the bottom of the stack, and return balance current for the ninth cell from the bottom of the stack
VC79AISense voltage input pin for the seventh cell from the bottom of the stack, balance current input for the seventh cell from the bottom of the stack, and return balance current for the eighth cell from the bottom of the stack
VC610AISense voltage input pin for the sixth cell from the bottom of the stack, balance current input for the sixth cell from the bottom of the stack, and return balance current for the seventh cell from the bottom of the stack
VC511AISense voltage input pin for the fifth cell from the bottom of the stack, balance current input for the fifth cell from the bottom of the stack, and return balance current for the sixth cell from the bottom of the stack
VC412AISense voltage input pin for the fourth cell from the bottom of the stack, balance current input for the fourth cell from the bottom of the stack, and return balance current for the fifth cell from the bottom of the stack
VC313AISense voltage input pin for the third cell from the bottom of the stack, balance current input for the third cell from the bottom of the stack, and return balance current for the fourth cell from the bottom of the stack
VC214AISense voltage input pin for the second cell from the bottom of the stack, balance current input for the second cell from the bottom of the stack, and return balance current for the third cell from the bottom of the stack
VC115AISense voltage input pin for the first cell from the bottom of the stack, balance current input for the first cell from the bottom of the stack, and return balance current for the second cell from the bottom of the stack
VC016AISense voltage input pin for the negative terminal of the first cell from the bottom of the stack, and return balance current for the first cell from the bottom of the stack
SRP17AIAnalog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN, where SRP is the top of the sense resistor. A charging current generates a positive voltage at SRP relative to SRN
NC18NCThis pin is not connected to silicon
SRN19AIAnalog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN, where SRN is the bottom of the sense resistor. A charging current generates a positive voltage at SRP relative to SRN
DFETOFF_LED420I/ODFETOFF input to keep the DFET off as long as this pin is asserted, or LED4 open drain output pin with current sink.
CFETOFF_LED321I/OCFETOFF input to keep the CFET off as long as this pin is asserted, or LED3 open drain output pin with current sink,
DCHG_LED2 22ODCHG output to indicate protection faults which should cause CFET to be off, or LED2 open drain output pin with current sink.
DDSG_LED123ODDSG output to indicate protection faults which should cause DFET to be off, or LED1 open drain output pin with current sink.
WAKE24AIPush-down button input to wake up the device from Shutdown or Hibernate mode.
RST_SD25AIInput pin for reset or shutdown
RADC3_TS326AIGeneral-purpose ADC or thermistor input
RADC2_TS227AIGeneral-purpose ADC or thermistor input
RADC1_TS128AIGeneral-purpose ADC or thermistor input
RADC0_TS029AIGeneral-purpose ADC or thermistor input
REG1830POInternal 1.8V LDO Output Cap Connection (only for internal use)
REG13531POInternal 1.35V LDO Output Cap Connection (only for internal use)
REGIO32PIInternal 3.3V/1.8V LDO Output Cap Connection (only for internal use)
NC33NCThis pin is not connected to silicon
RA0_SDA034I/OGeneral-purpose input with or without INT, or multifunction open-drain output, can be configured as SDA, SCL, SMBD, or SMBC
RA1_SCL035I/OGeneral-purpose input with or without INT, or multifunction open-drain output, can be configured as SDA, SCL, SMBD, or SMBC
RC036I/OGeneral-purpose digital input with or without INT, or multifunction push-pull output.
RC137I/OGeneral-purpose digital input with or without INT, or multifunction push-pull output.
RC238I/OGeneral-purpose digital input with or without INT, or multifunction push-pull output.
RC339I/OGeneral-purpose digital input with or without INT, or multifunction push-pull output.
RC440I/OGeneral-purpose digital input with or without INT, or multifunction push-pull output.
RC5_ALERT41I/OGeneral-purpose digital input with or without INT, or multifunction push-pull output. Defaults to ALERT output to signal general fault detection.
RC6_DISP42I/OGeneral-purpose digital input with or without INT, or multifunction push-pull output. Defaults to DISPbottom control output signal.
RC7_PRES43I/OGeneral-purpose digital input with or without INT, or multifunction push-pull output. Defaults to PRES for battery presence input signal.
RC8_INT44I/OGeneral-purpose digital input with or without INT, or multifunction push-pull output
NC45NCThis pin is not connected to silicon
NC46NCThis pin is not connected to silicon
RA2_SDA147IOGeneral-purpose input or multifunction open-drain output, can be configured as SDA, SCL, SMBD, or SMBC
RA3_SCL148IOGeneral-purpose input or multifunction open-drain output, can be configured as SDA, SCL, SMBD, or SMBC
VSS49PDevice ground
NC50NCThis pin is not connected to silicon
FUSE51IO,AFuse sense and drive
REGOUT52AOExternal LDO output, which can be programmed for 2 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V
REGIN53AIInput pin for external LDO REGOUT
BREG54AOBase control signal for external regulatory transistor
LD55AILoad detect pin
PACK56AIPack sense input pin
PDSG57AOPre-discharge control pin
DSG58AODischarge control pin
VCC59PSecondary power supply input
PCHG60AOPre-charge control pin
CHG61AOCharge control pin
CP62AOCharge pump capacitor
BAT63PPrimary power supply input from battery
VC1664AISense voltage input pin for the sixteenth cell from the bottom of the stack, and balance current input for the sixteenth cell from the bottom of the stack
(1) I = Input, O = Output, I/O = Input or Output, AI = Analog Input, AO = Analog Output, G = Ground, P = Power.