SBASAO8 June   2025 DAC39RF20

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI Interface Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RF Mode
        3. 7.3.1.3 DES Modes
      2. 7.3.2  DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3  DEM and Dither
      4. 7.3.4  Offset Adjustment
      5. 7.3.5  Clocking Subsystem
        1. 7.3.5.1 Converter Phase Locked Loop (CPLL)
        2. 7.3.5.2 Clock and SYSREF Delay
        3. 7.3.5.3 SYSREF Capture and Monitoring
          1. 7.3.5.3.1 SYSREF Frequency Requirements
          2. 7.3.5.3.2 SYSREF Pulses for Full Alignment
          3. 7.3.5.3.3 Automatic SYSREF Calibration and Tracking
            1. 7.3.5.3.3.1 SYSREF Automatic Calibration Procedure
            2. 7.3.5.3.3.2 Multi-device Alignment
            3. 7.3.5.3.3.3 Calibration Failure
            4. 7.3.5.3.3.4 SYSREF Tracking
        4. 7.3.5.4 Trigger Clocking
      6. 7.3.6  Digital Signal Processing Blocks
        1. 7.3.6.1  Bypass Mode
        2. 7.3.6.2  DUC Mode
          1. 7.3.6.2.1 Digital Upconverter (DUC)
            1. 7.3.6.2.1.1 Interpolation Filters
            2. 7.3.6.2.1.2 Numerically Controlled Oscillator (NCO)
              1. 7.3.6.2.1.2.1 Phase-continuous NCO Update Mode
              2. 7.3.6.2.1.2.2 Phase-coherent NCO Update Mode
              3. 7.3.6.2.1.2.3 Phase-sync NCO Update Mode
              4. 7.3.6.2.1.2.4 NCO Synchronization
                1. 7.3.6.2.1.2.4.1 JESD204C LSB Synchronization
        3. 7.3.6.3  DDS SPI Mode
        4. 7.3.6.4  DDS Vector Mode
          1. 7.3.6.4.1 Second Order Amplitude Support
          2. 7.3.6.4.2 Vector Order and Symmetric Vector Mode
          3. 7.3.6.4.3 Initial Startup
          4. 7.3.6.4.4 Trigger Queuing
          5. 7.3.6.4.5 Trigger Burst
          6. 7.3.6.4.6 Hold Mode
          7. 7.3.6.4.7 Indexing Mode
          8. 7.3.6.4.8 Queued or Burst Triggers in Indexing-Mode
          9. 7.3.6.4.9 Writing Vectors While DDS is Enabled
        5. 7.3.6.5  DDS Streaming Mode
        6. 7.3.6.6  DSP Triggering
          1. 7.3.6.6.1 Trigger Latency
        7. 7.3.6.7  NCO Square Wave Mode
          1. 7.3.6.7.1 Square Wave Enable
        8. 7.3.6.8  DSP Mute Function
        9. 7.3.6.9  DSP Output Gain
        10. 7.3.6.10 Complex Output Support
        11. 7.3.6.11 Channel Bonder
        12. 7.3.6.12 Programmable FIR Filter
          1. 7.3.6.12.1 PFIR Coefficients
          2. 7.3.6.12.2 PFIR Reflection Cancellation Mode
          3. 7.3.6.12.3 PFIR Power Savings
          4. 7.3.6.12.4 PFIR Usage
        13. 7.3.6.13 DES Interpolator
          1. 7.3.6.13.1 DAC Mute Function
      7. 7.3.7  Serdes Physical Layer
        1. 7.3.7.1 Serdes PLL
          1. 7.3.7.1.1 Enabling the Serdes PLL
          2. 7.3.7.1.2 Reference Clock
          3. 7.3.7.1.3 PLL VCO Calibration
          4. 7.3.7.1.4 Serdes PLL Loop Bandwidth
        2. 7.3.7.2 Serdes Receiver
          1. 7.3.7.2.1 Serdes Data Rate Selection
          2. 7.3.7.2.2 Serdes Receiver Termination
          3. 7.3.7.2.3 Serdes Receiver Polarity
          4. 7.3.7.2.4 Serdes Clock Data Recovery
          5. 7.3.7.2.5 Serdes Equalizer
            1. 7.3.7.2.5.1 Adaptive Equalization
            2. 7.3.7.2.5.2 Fixed Equalization
            3. 7.3.7.2.5.3 Pre and Post Cursor Analysis
          6. 7.3.7.2.6 Serdes Receiver Eyescan
            1. 7.3.7.2.6.1 Eyescan Procedure
            2. 7.3.7.2.6.2 Building an Eye Diagram
        3. 7.3.7.3 Serdes PHY Status
      8. 7.3.8  JESD204C Interface
        1. 7.3.8.1 Deviation from JESD204C Standard
        2. 7.3.8.2 Link Layer
          1. 7.3.8.2.1 Serdes Crossbar
          2. 7.3.8.2.2 Bit Error Rate Tester
          3. 7.3.8.2.3 Scrambler and Descrambler
          4. 7.3.8.2.4 64b and 66b Decoding Link Layer
            1. 7.3.8.2.4.1 Sync Header Alignment
            2. 7.3.8.2.4.2 Extended Multiblock Alignment
            3. 7.3.8.2.4.3 Data Integrity
          5. 7.3.8.2.5 8B and 10B Encoding Link Layer
            1. 7.3.8.2.5.1 Code Group Synchronization (CGS)
            2. 7.3.8.2.5.2 Initial Lane Alignment Sequence (ILAS)
            3. 7.3.8.2.5.3 Multi-frames and the Local Multiframe Clock (LMFC)
            4. 7.3.8.2.5.4 Frame and Multiframe Monitoring
            5. 7.3.8.2.5.5 Link Restart
            6. 7.3.8.2.5.6 Link Error Reports
            7. 7.3.8.2.5.7 Watchdog Timer (JTIMER)
        3. 7.3.8.3 SYSREF Alignment Required in Subclass 1 Mode
        4. 7.3.8.4 Transport Layer
        5. 7.3.8.5 JESD204C Debug Capture (JCAP)
          1. 7.3.8.5.1 Physical Layer Debug Capture
          2. 7.3.8.5.2 Link Layer Debug Capture
          3. 7.3.8.5.3 Transport Layer Debug Capture
        6. 7.3.8.6 JESD204C Interface Modes
          1. 7.3.8.6.1 JESD204C Format Diagrams
            1. 7.3.8.6.1.1 16-bit Formats
            2. 7.3.8.6.1.2 12-bit Formats
            3. 7.3.8.6.1.3 8-bit Formats
          2. 7.3.8.6.2 DUC and DDS Modes
      9. 7.3.9  Data Path Latency
      10. 7.3.10 Multi-Device Synchronization and Deterministic Latency
        1. 7.3.10.1 Programming RBD
        2. 7.3.10.2 Multiframe Lengths less than 32 Octa-Bytes (256 Bytes)
        3. 7.3.10.3 Recommended Algorithm to Determine the RBD Value
        4. 7.3.10.4 Operation in Subclass 0 Systems
      11. 7.3.11 Link Reset
      12. 7.3.12 Alarm Generation
        1. 7.3.12.1 Over Range Detection
        2. 7.3.12.2 Over Range Masking
      13. 7.3.13 Mute Function
        1. 7.3.13.1 Alarm Data Path Muting
        2. 7.3.13.2 Transmit Enables
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
  9. 8 Programming
    1. 8.1 Using the Standard SPI Interface
      1. 8.1.1 SCS
      2. 8.1.2 SCLK
      3. 8.1.3 SDI
      4. 8.1.4 SDO
      5. 8.1.5 Serial Interface Protocol
      6. 8.1.6 Streaming Mode
    2. 8.2 Using the Fast Reconfiguration Interface
    3. 8.3 Register Maps
      1. 8.3.1  Standard_SPI-3.1 Registers
      2. 8.3.2  System Registers
      3. 8.3.3  Trigger Registers
      4. 8.3.4  CPLL_AND_CLOCK Registers
      5. 8.3.5  SYSREF Registers
      6. 8.3.6  JESD204C Registers
      7. 8.3.7  JESD204C_Advanced Registers
      8. 8.3.8  SerDes_Equalizer Registers
      9. 8.3.9  SerDes_Eye-Scan Registers
      10. 8.3.10 SerDes_Lane_Status Registers
      11. 8.3.11 SerDes_PLL Registers
      12. 8.3.12 DAC_and_Analog_Configuration Registers
      13. 8.3.13 Datapath Registers
      14. 8.3.14 NCO_and_Mixer Registers
      15. 8.3.15 Alarm Registers
      16. 8.3.16 Fuse_Control Registers
      17. 8.3.17 Fuse_Backed Registers
      18. 8.3.18 DDS_Vector_Mode Registers
      19. 8.3.19 Programmable_FIR Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Startup Procedure
      2. 9.1.2 Bandwidth Optimization for Square Wave Mode
    2. 9.2 Typical Application: Ku-Band Radar Transmitter
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Up and Down Sequence
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines and Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.14 NCO_and_Mixer Registers

Table 8-249 lists the memory-mapped registers for the NCO_and_Mixer registers. All register offset addresses not listed in Table 8-249 should be considered as reserved locations and the register contents should not be modified.

Table 8-249 NCO_AND_MIXER Registers
OffsetAcronymRegister NameSection
0x300NCO_CNTLSection 8.3.14.1
0x301NCO_CONTSection 8.3.14.2
0x303NCO_ARSection 8.3.14.3
0x304STREAM_MODESection 8.3.14.4
0x305NCO_SSSection 8.3.14.5
0x306NCO_SQ_MODESection 8.3.14.6
0x307NCO_SQ_ENSection 8.3.14.7
0x308NCO_SQ_SELSection 8.3.14.8
0x320FREQ_0Section 8.3.14.9
0x328FREQ_1Section 8.3.14.10
0x330FREQ_2Section 8.3.14.11
0x338FREQ_3Section 8.3.14.12
0x340PHASE_0Section 8.3.14.13
0x342PHASE_1Section 8.3.14.14
0x344PHASE_2Section 8.3.14.15
0x346PHASE_3Section 8.3.14.16
0x348AMP_0Section 8.3.14.17
0x34AAMP_1Section 8.3.14.18
0x34CAMP_2Section 8.3.14.19
0x34EAMP_3Section 8.3.14.20
0x360SLEW0Section 8.3.14.21
0x361SLEW1Section 8.3.14.22
0x362SLEW2Section 8.3.14.23
0x363SLEW3Section 8.3.14.24
0x364DUTY_CYCLE0Section 8.3.14.25
0x366DUTY_CYCLE1Section 8.3.14.26
0x368DUTY_CYCLE2Section 8.3.14.27
0x36ADUTY_CYCLE3Section 8.3.14.28
0x370FREQ_R_0Section 8.3.14.29
0x378FREQ_R_1Section 8.3.14.30
0x380FREQ_R_2Section 8.3.14.31
0x388FREQ_R_3Section 8.3.14.32
0x390PHASE_R_0Section 8.3.14.33
0x392PHASE_R_1Section 8.3.14.34
0x394PHASE_R_2Section 8.3.14.35
0x396PHASE_R_3Section 8.3.14.36
0x398AMP_R_0Section 8.3.14.37
0x39AAMP_R_1Section 8.3.14.38
0x39CAMP_R_2Section 8.3.14.39
0x39EAMP_R_3Section 8.3.14.40

Complex bit access types are encoded to fit into small table cells. Table 8-250 shows the codes that are used for access types in this section.

Table 8-250 NCO_and_Mixer Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.3.14.1 NCO_CNTL Register (Offset = 0x300) [Reset = 0x00]

NCO_CNTL is shown in Table 8-251.

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Table 8-251 NCO_CNTL Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR0x0
2NCO_SCR/W0x0 Self-Coherent NCO Mode: If this bit is set, all NCOs use the reference counter from the NCO in DDS/DUC channel 0. This is typically used along with the NCO_SS register. This only impacts phase-coherent mode (NCO_CONT=0).
1RESERVEDR0x0
0NCO_ENR/W0x0 When set, DUC samples are mixed with the NCO. When cleared, the mixer is bypassed. This only applies to DUC mode and has no effect on DDS modes (see DSP_MODE).

8.3.14.2 NCO_CONT Register (Offset = 0x301) [Reset = 0x00]

NCO_CONT is shown in Table 8-252.

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Table 8-252 NCO_CONT Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0NCO_CONTR/W0x0 For each bit NCO_CONT[n], if set, NCOn operates in phase-continuous mode. This means that frequency changes occur without seeding the phase accumulator. If the bit is clear, NCOn operates in phase-coherent mode. During frequency changes, the phase accumulator is seeded from a master counter. This means that if changing from frequency A to B and then back to A, the phase returns to what it would have been if the change never occurred. NCO_CONT only applies to DUC mode and DDS SPI mode (see DSP_MODE).

8.3.14.3 NCO_AR Register (Offset = 0x303) [Reset = 0x00]

NCO_AR is shown in Table 8-253.

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Table 8-253 NCO_AR Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0NCO_ARR/W0x0 For each bit NCO_AR[n], if set, the accumulator for NCOn will be reset on every trigger event directed to DSPn. NCO_AR only applies to DUC mode and DDS Stream Mode (see DSP_MODE). See DSP Triggering

8.3.14.4 STREAM_MODE Register (Offset = 0x304) [Reset = 0x00]

STREAM_MODE is shown in Table 8-254.

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Table 8-254 STREAM_MODE Register Field Descriptions
BitFieldTypeResetDescription
7-6STREAM_MODE3R/W0x0 STREAM_MODEn configures the streaming mode for DSPn. This applies only to DSP channels configured for DDS Stream Mode.
Note: This register should only be changed when SYS_EN=0.
  • 0x0 = Dynamically stream frequency/phase/amplitude using the sdata[0] control bit.
  • 0x1 = Only stream frequency samples (sdata[0] is the frequency LSB). Phase and amplitude are set by the PHASE[n] and AMP[n] registers.
  • 0x2 = Only stream phase/amplitude samples (sdata[0] is ignored). Frequency is set by the FREQ[n] register.
  • 0x3 = Reserved
5-4STREAM_MODE2R/W0x0 see STREAM_MODE3
3-2STREAM_MODE1R/W0x0 see STREAM_MODE3
1-0STREAM_MODE0R/W0x0 see STREAM_MODE3

8.3.14.5 NCO_SS Register (Offset = 0x305) [Reset = 0x00]

NCO_SS is shown in Table 8-255.

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Table 8-255 NCO_SS Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0
0NCO_SSR/W0x0 If this bit is set, all NCOs will continuously self-synchronize every 256 DAC clock cycles. Most applications will not use this, but in a radiation environment, the user can set NCO_SS to continuously transfer the upset-immune AMP, FREQ and PHASE register values to the internal (non-immune) registers inside the NCOs. This is helpful for generating tones under radiation without the need for an external, periodic synchronization source (such as SYSREF).
NCO_SS can be changed while the NCOs are operating (SYS_EN=1). To write a new FREQ, AMP, or PHASE value, clear NCO_SS first, and then set it again after the new values are written. All values go into effect simultaneously on all NCOs.
The user should ensure that NCO_AR=0 whenever NCO_SS=1 (otherwise the NCO accumulators and/or reference counters keep getting reset).
If the user also sets NCO_SC=1 and NCO_CONT=0, then all four NCOs will maintain coherency with each other under radiation (but coherence with an external component is not guaranteed). Each NCO accumulator is continuously seeded from the reference counter in DUC/DDS channel 0. This feature can be used to generate coherent harmonic tones to cancel out harmonic distortion in the DAC.
This can be used for DUC mode, DDS SPI mode, and DDS Stream mode.

8.3.14.6 NCO_SQ_MODE Register (Offset = 0x306) [Reset = 0x00]

NCO_SQ_MODE is shown in Table 8-256.

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Table 8-256 NCO_SQ_MODE Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0NCO_SQ_MODER/W0x0 For each bit NCO_SQ_MODE[n], if set, the output of NCOn will produce a square waveform instead of a sine/cosine waveform. NCO_SQ_MODE only applies to DDS modes (see DSP_MODE). In this mode, the SLEW and DUTY_CYCLE registers can be used to customize the slew rate and duty cycle of the waveform. See NCO Square Wave Mode.
If a DSP channel is configured to produce a square wave, the user should bind that DSP exclusively to a DAC output (i.e. do not sum any other DSP channels into the same DAC).
Note: This register should only be changed when SYS_EN=0.

8.3.14.7 NCO_SQ_EN Register (Offset = 0x307) [Reset = 0x00]

NCO_SQ_EN is shown in Table 8-257.

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Table 8-257 NCO_SQ_EN Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0NCO_SQ_ENR/W0x0 If NCO_SQ_SELn = 0, then NCO_SQ_EN[n] acts as the enable signal for the square wave output of NCOn. See Square Wave Enable.

8.3.14.8 NCO_SQ_SEL Register (Offset = 0x308) [Reset = 0x0000]

NCO_SQ_SEL is shown in Table 8-258.

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Table 8-258 NCO_SQ_SEL Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0x0
14-12NCO_SQ_SEL3R/W0x0 NCO_SQ_SELn selects which pin or register will act as the waveform enable for NCOn. Applies only to NCO Square Wave Mode. See also Square Wave Enable.
Note 1: These settings always uses a physical TRIG pin, even if SYNCB_PIN_FUNC is assigning SYNCB as an alternate input for a TRIG pin.
Note 2: The SYNCB input is active high in this mode. When using NCO_SQ_SELn=5, ensure that JENC=1 and SYNCB_PIN_FUNC=0.
  • 0x0 = register bit (default)
  • 0x1 = TRIG0 pin (note 1)
  • 0x2 = TRIG1 pin (note 1)
  • 0x3 = TRIG2 pin (note 1)
  • 0x4 = TRIG3 pin (note 1)
  • 0x5 = SYNCB pin (note 2)
  • 0x6 = Reserved
  • 0x7 = Reserved
11RESERVEDR0x0
8RESERVEDR0x0
10-8NCO_SQ_SEL2R/W0x0 See NCO_SQ_SEL3
7RESERVEDR0x0
6-4NCO_SQ_SEL1R/W0x0 See NCO_SQ_SEL3
3RESERVEDR0x0
2-0NCO_SQ_SEL0R/W0x0 See NCO_SQ_SEL3

8.3.14.9 FREQ_0 Register (Offset = 0x320) [Reset = 0x0000000000000000]

FREQ_0 is shown in Table 8-259.

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Table 8-259 FREQ_0 Register Field Descriptions
BitFieldTypeResetDescription
63-0FREQ[0]R/W0x0 Specifies the frequency for NCO0. Used in DUC mode, DDS SPI mode, and DDS Stream (phase) mode.
The NCO frequency (FNCO) is:
FNCO = FREQ[0] * 2-64 * FDACCLK
FDACCLK is the sample frequency of the DAC. FREQ[0] is the integer value of this register. This register can be interpreted as signed or unsigned (both interpretations are valid).
Use this equation to determine the value to program:
FREQ[0] = 264 * FNCO /FDACCLK
Note: Changes to this register do not take effect until DSP0 receives a trigger (see DSP Triggering).
Note: FREQ[0] should not be updated inside a window of +-320 DAC cycles around the initiation of a trigger event on DSP0.

8.3.14.10 FREQ_1 Register (Offset = 0x328) [Reset = 0x0000000000000000]

FREQ_1 is shown in Table 8-260.

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Table 8-260 FREQ_1 Register Field Descriptions
BitFieldTypeResetDescription
63-0FREQ[1]R/W0x0 See FREQ[0]

8.3.14.11 FREQ_2 Register (Offset = 0x330) [Reset = 0x0000000000000000]

FREQ_2 is shown in Table 8-261.

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Table 8-261 FREQ_2 Register Field Descriptions
BitFieldTypeResetDescription
63-0FREQ[2]R/W0x0 See FREQ[0]

8.3.14.12 FREQ_3 Register (Offset = 0x338) [Reset = 0x0000000000000000]

FREQ_3 is shown in Table 8-262.

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Table 8-262 FREQ_3 Register Field Descriptions
BitFieldTypeResetDescription
63-0FREQ[3]R/W0x0 See FREQ[0]

8.3.14.13 PHASE_0 Register (Offset = 0x340) [Reset = 0x0000]

PHASE_0 is shown in Table 8-263.

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Table 8-263 PHASE_0 Register Field Descriptions
BitFieldTypeResetDescription
15-0PHASE[0]R/W0x0 Specifies the phase for NCOn. Used in DUC mode, DDS SPI Mode, and DDS Stream (frequency) mode.
This value is left justified into a 64-bit field and then added to the phase accumulator. The phase (in radians) is PHASE[0] * 2-16 * 2Ï€. This register can be interpreted as signed or unsigned.
Note: Changes to this register do not take effect until DSP0 receives a trigger (see DSP Triggering).
Note: PHASE[0] should not be updated inside a window of +-320 DAC cycles around the initiation of a trigger event on DSP0.

8.3.14.14 PHASE_1 Register (Offset = 0x342) [Reset = 0x0001]

PHASE_1 is shown in Table 8-264.

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Table 8-264 PHASE_1 Register Field Descriptions
BitFieldTypeResetDescription
15-0PHASE[1]R/W0x1 See PHASE[0]

8.3.14.15 PHASE_2 Register (Offset = 0x344) [Reset = 0x0002]

PHASE_2 is shown in Table 8-265.

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Table 8-265 PHASE_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0PHASE[2]R/W0x2 See PHASE[0]

8.3.14.16 PHASE_3 Register (Offset = 0x346) [Reset = 0x0003]

PHASE_3 is shown in Table 8-266.

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Table 8-266 PHASE_3 Register Field Descriptions
BitFieldTypeResetDescription
15-0PHASE[3]R/W0x3 See PHASE[0]

8.3.14.17 AMP_0 Register (Offset = 0x348) [Reset = 0x0000]

AMP_0 is shown in Table 8-267.

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Table 8-267 AMP_0 Register Field Descriptions
BitFieldTypeResetDescription
15-0AMP[0]R/W0x0 Specifies the DDS amplitude for DSP (DDS) channel 0. 16-bit signed value.
This register applies to DDS SPI Mode and DDS Stream Mode (see DSP_MODE). For DDS Stream mode, this register is only used when AMP_STREAM=0.
Note: Changes to this register do not take effect until DSP0 receives a trigger (see DSP Triggering).
Note: AMP[0] should not be updated inside a window of +-320 DAC cycles around the initiation of a trigger event on DSP0.

8.3.14.18 AMP_1 Register (Offset = 0x34A) [Reset = 0x0000]

AMP_1 is shown in Table 8-268.

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Table 8-268 AMP_1 Register Field Descriptions
BitFieldTypeResetDescription
15-0AMP[1]R/W0x0 See AMP[0]

8.3.14.19 AMP_2 Register (Offset = 0x34C) [Reset = 0x0000]

AMP_2 is shown in Table 8-269.

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Table 8-269 AMP_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0AMP[2]R/W0x0 See AMP[0]

8.3.14.20 AMP_3 Register (Offset = 0x34E) [Reset = 0x0000]

AMP_3 is shown in Table 8-270.

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Table 8-270 AMP_3 Register Field Descriptions
BitFieldTypeResetDescription
15-0AMP[3]R/W0x0 See AMP[0]

8.3.14.21 SLEW0 Register (Offset = 0x360) [Reset = 0x00]

SLEW0 is shown in Table 8-271.

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Table 8-271 SLEW0 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0SLEW0R/W0x0 Specifies the slew time for DDS square waves for DDS channel n. Applies only to NCO Square Wave Mode. The legal range is from 0 to 9. Higher values produce a faster slew rate (shorter slew time).
The slew time in degrees is: 90*2-SLEW0
The slew time in radians is: 0.5Ï€*2-SLEW
The slew time in seconds is: 0.25*2-SLEW0 / FNCONote: Changes to this register take effect when DSP0 receives a trigger (see DSP Triggering), or while the square wave output is gated low. See Square Wave Enable.

8.3.14.22 SLEW1 Register (Offset = 0x361) [Reset = 0x00]

SLEW1 is shown in Table 8-272.

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Table 8-272 SLEW1 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0SLEW1R/W0x0 See SLEW0

8.3.14.23 SLEW2 Register (Offset = 0x362) [Reset = 0x00]

SLEW2 is shown in Table 8-273.

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Table 8-273 SLEW2 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0SLEW2R/W0x0 See SLEW0

8.3.14.24 SLEW3 Register (Offset = 0x363) [Reset = 0x00]

SLEW3 is shown in Table 8-274.

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Table 8-274 SLEW3 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0SLEW3R/W0x0 See SLEW0

8.3.14.25 DUTY_CYCLE0 Register (Offset = 0x364) [Reset = 0x0800]

DUTY_CYCLE0 is shown in Table 8-275.

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Table 8-275 DUTY_CYCLE0 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0x0
11-0DUTY_CYCLE0R/W0x800 Specifies the duty cycle for DDS square waves for DDS channel n. Applies only to NCO Square Wave Mode. The default value (2048 decimal) provides a duty cycle of 50%.The duty cycle (in percent) is equal to 100% * DUTY_CYCLE0/4096brbr#Note: Changes to this register take effect when DSP0 receives a trigger (see DSP Triggering), or while the square wave output is gated low. See Square Wave Enable.

8.3.14.26 DUTY_CYCLE1 Register (Offset = 0x366) [Reset = 0x0800]

DUTY_CYCLE1 is shown in Table 8-276.

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Table 8-276 DUTY_CYCLE1 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0x0
11-0DUTY_CYCLE1R/W0x800 See DUTY_CLCYE0

8.3.14.27 DUTY_CYCLE2 Register (Offset = 0x368) [Reset = 0x0800]

DUTY_CYCLE2 is shown in Table 8-277.

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Table 8-277 DUTY_CYCLE2 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0x0
11-0DUTY_CYCLE2R/W0x800 See DUTY_CLCYE0

8.3.14.28 DUTY_CYCLE3 Register (Offset = 0x36A) [Reset = 0x0800]

DUTY_CYCLE3 is shown in Table 8-278.

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Table 8-278 DUTY_CYCLE3 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0x0
11-0DUTY_CYCLE3R/W0x800 See DUTY_CLCYE0

8.3.14.29 FREQ_R_0 Register (Offset = 0x370) [Reset = 0xXXXXXXXXXXXXXXXX]

FREQ_R_0 is shown in Table 8-279.

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Table 8-279 FREQ_R_0 Register Field Descriptions
BitFieldTypeResetDescription
63-0FREQ_R[0]RX This provides a readback of the frequency setting that is currently in use by DUC/DDS channel 0. The frequency could be determined by the FREQ register or another source. The value is sampled as each byte is read, so it may return incoherent data if the frequency changes during readback.

8.3.14.30 FREQ_R_1 Register (Offset = 0x378) [Reset = 0xXXXXXXXXXXXXXXXX]

FREQ_R_1 is shown in Table 8-280.

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Table 8-280 FREQ_R_1 Register Field Descriptions
BitFieldTypeResetDescription
63-0FREQ_R[1]RX See FREQ_R[0]

8.3.14.31 FREQ_R_2 Register (Offset = 0x380) [Reset = 0xXXXXXXXXXXXXXXXX]

FREQ_R_2 is shown in Table 8-281.

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Table 8-281 FREQ_R_2 Register Field Descriptions
BitFieldTypeResetDescription
63-0FREQ_R[2]RX See FREQ_R[0]

8.3.14.32 FREQ_R_3 Register (Offset = 0x388) [Reset = 0xXXXXXXXXXXXXXXXX]

FREQ_R_3 is shown in Table 8-282.

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Table 8-282 FREQ_R_3 Register Field Descriptions
BitFieldTypeResetDescription
63-0FREQ_R[3]RX See FREQ_R[0]

8.3.14.33 PHASE_R_0 Register (Offset = 0x390) [Reset = 0xXXXX]

PHASE_R_0 is shown in Table 8-283.

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Table 8-283 PHASE_R_0 Register Field Descriptions
BitFieldTypeResetDescription
15-0PHASE_R[0]RX This provides a readback of the phase setting that is currently in use by DUC/DDS channel 0. The phase could be determined by the PHASE register or another source. The value is sampled as each byte is read, so it may return incoherent data if the phase changes during readback.

8.3.14.34 PHASE_R_1 Register (Offset = 0x392) [Reset = 0xXXXX]

PHASE_R_1 is shown in Table 8-284.

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Table 8-284 PHASE_R_1 Register Field Descriptions
BitFieldTypeResetDescription
15-0PHASE_R[1]RX See PHASE_R[0]

8.3.14.35 PHASE_R_2 Register (Offset = 0x394) [Reset = 0xXXXX]

PHASE_R_2 is shown in Table 8-285.

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Table 8-285 PHASE_R_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0PHASE_R[2]RX See PHASE_R[0]

8.3.14.36 PHASE_R_3 Register (Offset = 0x396) [Reset = 0xXXXX]

PHASE_R_3 is shown in Table 8-286.

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Table 8-286 PHASE_R_3 Register Field Descriptions
BitFieldTypeResetDescription
15-0PHASE_R[3]RX See PHASE_R[0]

8.3.14.37 AMP_R_0 Register (Offset = 0x398) [Reset = 0xXXXX]

AMP_R_0 is shown in Table 8-287.

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Table 8-287 AMP_R_0 Register Field Descriptions
BitFieldTypeResetDescription
15-0AMP_R[0]RX This provides a readback of the amplitude setting that is currently in use by DDS channel 0. Format is 16-bit signed. The amplitude could be determined by the AMP register or another source. In non-DDS modes, the return value is undefined. The value is sampled as each byte is read, so it may return incoherent data if the amplitude changes during readback.

8.3.14.38 AMP_R_1 Register (Offset = 0x39A) [Reset = 0xXXXX]

AMP_R_1 is shown in Table 8-288.

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Table 8-288 AMP_R_1 Register Field Descriptions
BitFieldTypeResetDescription
15-0AMP_R[1]RX See Amp_R[0]

8.3.14.39 AMP_R_2 Register (Offset = 0x39C) [Reset = 0xXXXX]

AMP_R_2 is shown in Table 8-289.

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Table 8-289 AMP_R_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0AMP_R[2]RX See Amp_R[0]

8.3.14.40 AMP_R_3 Register (Offset = 0x39E) [Reset = 0xXXXX]

AMP_R_3 is shown in Table 8-290.

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Table 8-290 AMP_R_3 Register Field Descriptions
BitFieldTypeResetDescription
15-0AMP_R[3]RX See Amp_R[0]