SBASAO8 June   2025 DAC39RF20

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI Interface Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RF Mode
        3. 7.3.1.3 DES Modes
      2. 7.3.2  DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3  DEM and Dither
      4. 7.3.4  Offset Adjustment
      5. 7.3.5  Clocking Subsystem
        1. 7.3.5.1 Converter Phase Locked Loop (CPLL)
        2. 7.3.5.2 Clock and SYSREF Delay
        3. 7.3.5.3 SYSREF Capture and Monitoring
          1. 7.3.5.3.1 SYSREF Frequency Requirements
          2. 7.3.5.3.2 SYSREF Pulses for Full Alignment
          3. 7.3.5.3.3 Automatic SYSREF Calibration and Tracking
            1. 7.3.5.3.3.1 SYSREF Automatic Calibration Procedure
            2. 7.3.5.3.3.2 Multi-device Alignment
            3. 7.3.5.3.3.3 Calibration Failure
            4. 7.3.5.3.3.4 SYSREF Tracking
        4. 7.3.5.4 Trigger Clocking
      6. 7.3.6  Digital Signal Processing Blocks
        1. 7.3.6.1  Bypass Mode
        2. 7.3.6.2  DUC Mode
          1. 7.3.6.2.1 Digital Upconverter (DUC)
            1. 7.3.6.2.1.1 Interpolation Filters
            2. 7.3.6.2.1.2 Numerically Controlled Oscillator (NCO)
              1. 7.3.6.2.1.2.1 Phase-continuous NCO Update Mode
              2. 7.3.6.2.1.2.2 Phase-coherent NCO Update Mode
              3. 7.3.6.2.1.2.3 Phase-sync NCO Update Mode
              4. 7.3.6.2.1.2.4 NCO Synchronization
                1. 7.3.6.2.1.2.4.1 JESD204C LSB Synchronization
        3. 7.3.6.3  DDS SPI Mode
        4. 7.3.6.4  DDS Vector Mode
          1. 7.3.6.4.1 Second Order Amplitude Support
          2. 7.3.6.4.2 Vector Order and Symmetric Vector Mode
          3. 7.3.6.4.3 Initial Startup
          4. 7.3.6.4.4 Trigger Queuing
          5. 7.3.6.4.5 Trigger Burst
          6. 7.3.6.4.6 Hold Mode
          7. 7.3.6.4.7 Indexing Mode
          8. 7.3.6.4.8 Queued or Burst Triggers in Indexing-Mode
          9. 7.3.6.4.9 Writing Vectors While DDS is Enabled
        5. 7.3.6.5  DDS Streaming Mode
        6. 7.3.6.6  DSP Triggering
          1. 7.3.6.6.1 Trigger Latency
        7. 7.3.6.7  NCO Square Wave Mode
          1. 7.3.6.7.1 Square Wave Enable
        8. 7.3.6.8  DSP Mute Function
        9. 7.3.6.9  DSP Output Gain
        10. 7.3.6.10 Complex Output Support
        11. 7.3.6.11 Channel Bonder
        12. 7.3.6.12 Programmable FIR Filter
          1. 7.3.6.12.1 PFIR Coefficients
          2. 7.3.6.12.2 PFIR Reflection Cancellation Mode
          3. 7.3.6.12.3 PFIR Power Savings
          4. 7.3.6.12.4 PFIR Usage
        13. 7.3.6.13 DES Interpolator
          1. 7.3.6.13.1 DAC Mute Function
      7. 7.3.7  Serdes Physical Layer
        1. 7.3.7.1 Serdes PLL
          1. 7.3.7.1.1 Enabling the Serdes PLL
          2. 7.3.7.1.2 Reference Clock
          3. 7.3.7.1.3 PLL VCO Calibration
          4. 7.3.7.1.4 Serdes PLL Loop Bandwidth
        2. 7.3.7.2 Serdes Receiver
          1. 7.3.7.2.1 Serdes Data Rate Selection
          2. 7.3.7.2.2 Serdes Receiver Termination
          3. 7.3.7.2.3 Serdes Receiver Polarity
          4. 7.3.7.2.4 Serdes Clock Data Recovery
          5. 7.3.7.2.5 Serdes Equalizer
            1. 7.3.7.2.5.1 Adaptive Equalization
            2. 7.3.7.2.5.2 Fixed Equalization
            3. 7.3.7.2.5.3 Pre and Post Cursor Analysis
          6. 7.3.7.2.6 Serdes Receiver Eyescan
            1. 7.3.7.2.6.1 Eyescan Procedure
            2. 7.3.7.2.6.2 Building an Eye Diagram
        3. 7.3.7.3 Serdes PHY Status
      8. 7.3.8  JESD204C Interface
        1. 7.3.8.1 Deviation from JESD204C Standard
        2. 7.3.8.2 Link Layer
          1. 7.3.8.2.1 Serdes Crossbar
          2. 7.3.8.2.2 Bit Error Rate Tester
          3. 7.3.8.2.3 Scrambler and Descrambler
          4. 7.3.8.2.4 64b and 66b Decoding Link Layer
            1. 7.3.8.2.4.1 Sync Header Alignment
            2. 7.3.8.2.4.2 Extended Multiblock Alignment
            3. 7.3.8.2.4.3 Data Integrity
          5. 7.3.8.2.5 8B and 10B Encoding Link Layer
            1. 7.3.8.2.5.1 Code Group Synchronization (CGS)
            2. 7.3.8.2.5.2 Initial Lane Alignment Sequence (ILAS)
            3. 7.3.8.2.5.3 Multi-frames and the Local Multiframe Clock (LMFC)
            4. 7.3.8.2.5.4 Frame and Multiframe Monitoring
            5. 7.3.8.2.5.5 Link Restart
            6. 7.3.8.2.5.6 Link Error Reports
            7. 7.3.8.2.5.7 Watchdog Timer (JTIMER)
        3. 7.3.8.3 SYSREF Alignment Required in Subclass 1 Mode
        4. 7.3.8.4 Transport Layer
        5. 7.3.8.5 JESD204C Debug Capture (JCAP)
          1. 7.3.8.5.1 Physical Layer Debug Capture
          2. 7.3.8.5.2 Link Layer Debug Capture
          3. 7.3.8.5.3 Transport Layer Debug Capture
        6. 7.3.8.6 JESD204C Interface Modes
          1. 7.3.8.6.1 JESD204C Format Diagrams
            1. 7.3.8.6.1.1 16-bit Formats
            2. 7.3.8.6.1.2 12-bit Formats
            3. 7.3.8.6.1.3 8-bit Formats
          2. 7.3.8.6.2 DUC and DDS Modes
      9. 7.3.9  Data Path Latency
      10. 7.3.10 Multi-Device Synchronization and Deterministic Latency
        1. 7.3.10.1 Programming RBD
        2. 7.3.10.2 Multiframe Lengths less than 32 Octa-Bytes (256 Bytes)
        3. 7.3.10.3 Recommended Algorithm to Determine the RBD Value
        4. 7.3.10.4 Operation in Subclass 0 Systems
      11. 7.3.11 Link Reset
      12. 7.3.12 Alarm Generation
        1. 7.3.12.1 Over Range Detection
        2. 7.3.12.2 Over Range Masking
      13. 7.3.13 Mute Function
        1. 7.3.13.1 Alarm Data Path Muting
        2. 7.3.13.2 Transmit Enables
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
  9. 8 Programming
    1. 8.1 Using the Standard SPI Interface
      1. 8.1.1 SCS
      2. 8.1.2 SCLK
      3. 8.1.3 SDI
      4. 8.1.4 SDO
      5. 8.1.5 Serial Interface Protocol
      6. 8.1.6 Streaming Mode
    2. 8.2 Using the Fast Reconfiguration Interface
    3. 8.3 Register Maps
      1. 8.3.1  Standard_SPI-3.1 Registers
      2. 8.3.2  System Registers
      3. 8.3.3  Trigger Registers
      4. 8.3.4  CPLL_AND_CLOCK Registers
      5. 8.3.5  SYSREF Registers
      6. 8.3.6  JESD204C Registers
      7. 8.3.7  JESD204C_Advanced Registers
      8. 8.3.8  SerDes_Equalizer Registers
      9. 8.3.9  SerDes_Eye-Scan Registers
      10. 8.3.10 SerDes_Lane_Status Registers
      11. 8.3.11 SerDes_PLL Registers
      12. 8.3.12 DAC_and_Analog_Configuration Registers
      13. 8.3.13 Datapath Registers
      14. 8.3.14 NCO_and_Mixer Registers
      15. 8.3.15 Alarm Registers
      16. 8.3.16 Fuse_Control Registers
      17. 8.3.17 Fuse_Backed Registers
      18. 8.3.18 DDS_Vector_Mode Registers
      19. 8.3.19 Programmable_FIR Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Startup Procedure
      2. 9.1.2 Bandwidth Optimization for Square Wave Mode
    2. 9.2 Typical Application: Ku-Band Radar Transmitter
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Up and Down Sequence
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines and Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.9 SerDes_Eye-Scan Registers

Table 8-206 lists the memory-mapped registers for the SerDes_Eye-Scan registers. All register offset addresses not listed in Table 8-206 should be considered as reserved locations and the register contents should not be modified.

Table 8-206 SERDES_EYE-SCAN Registers
OffsetAcronymRegister NameSection
0x1F0ESRUNSection 8.3.9.1
0x1F1ES_CNTLSection 8.3.9.2
0x1F2ESPOSection 8.3.9.3
0x1F3ESVOSection 8.3.9.4
0x1F4ESBSELSection 8.3.9.5
0x1F5ECOUNT_CLRSection 8.3.9.6

Complex bit access types are encoded to fit into small table cells. Table 8-207 shows the codes that are used for access types in this section.

Table 8-207 SerDes_Eye-Scan Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.3.9.1 ESRUN Register (Offset = 0x1F0) [Reset = 0x00]

ESRUN is shown in Table 8-208.

Return to the Summary Table.

Table 8-208 ESRUN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0
0ESRUNR/W0x0 After setting up eye-scan, set ESRUN=1 to run the eye-scan test. See Eye-Scan Usage Model.

8.3.9.2 ES_CNTL Register (Offset = 0x1F1) [Reset = 0x00]

ES_CNTL is shown in Table 8-209.

Return to the Summary Table.

Table 8-209 ES_CNTL Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0
5-4ESLENR/W0x0 Specify the length of the eye-scan test. Larger values will give more consistent results, but will take longer.
Note: Many eye-scan modes only analyze zeros (or ones). Since they dont analyze every sample, those modes will take longer to complete compared to a mode that analyzes all samples.
  • 0x0 = 127
  • 0x1 = 1032
  • 0x2 = 8191
  • 0x3 = 65535
3-0EYESCAN_MODER/W0x0 Specify the eye-scan mode. Applies to all lanes.
Note: Only change this register while ESRUN=0.
  • 0x0 = ES_DISABLED Eye-scan disabled (default).
  • 0x1 = ES_COMPARE Counts mismatches between the normal sampler and the eye-scan sampler. Analyzes zeros and ones.
  • 0x2 = ES_COMPAREZEROS Same as 0b0001, but only analyzes zeros.
  • 0x3 = ES_COMPAREONES Same as 0b0001, but only analyzes ones.
  • 0x4 = ES_COUNTONES Increments ECOUNT[n] when the eye-scan sample is 1.
  • 0x5 = RESERVED
  • 0x6 = RESERVED
  • 0x7 = RESERVED
  • 0x8 = ES_AVEZEROS Adjusts ESVO_S[n] to the average voltage for a zero.
  • 0x9 = ES_OUTERZEROS Adjusts ESVO_S[n] to the lowest voltage for a zero.
  • 0xA = ES_INNERZEROS Adjusts ESVO_Sn to the highest voltage for a zero.
  • 0xB = RESERVED
  • 0xC = ES_AVGONES Adjusts ESVO_Sn to the average voltage for a one.
  • 0xD = ES_OUTERONES Adjusts ESVO_Sn to the highest voltage for a one.
  • 0xE = ES_INNERONES Adjusts ESVO_Sn to the lowest voltage for a one.
  • 0xF = RESERVED

8.3.9.3 ESPO Register (Offset = 0x1F2) [Reset = 0x00]

ESPO is shown in Table 8-210.

Return to the Summary Table.

Table 8-210 ESPO Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0
6-0ESPOR/W0x0 Eye-scan phase offset for all lanes. This adjusts the sampling instant of the eye-scan sampler compared to the normal sampler. This is a signed value from -64 to +63 and the step size is 1/32th of a UI.
Note: Only change this register while ESRUN=0.

8.3.9.4 ESVO Register (Offset = 0x1F3) [Reset = 0x00]

ESVO is shown in Table 8-211.

Return to the Summary Table.

Table 8-211 ESVO Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0
5-0ESVOR/W0x0 Eye-scan voltage offset for all lanes. This adjusts the voltage threshold of the eye-scan sampler. This is a signed value from -32 to +31. The step size is about 10mV (giving an adjustment range of about -320mV to +310mV). This field is ignored for eye-scan modes that adjust the voltage offset automatically and return a result on ESVO_S[n].
Note: Only change this register while ESRUN=0.

8.3.9.5 ESBSEL Register (Offset = 0x1F4) [Reset = 0x00]

ESBSEL is shown in Table 8-212.

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Table 8-212 ESBSEL Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0x0
4-0ESBSELR/W0x0 Eye-scan only runs on every 32th bit (the PHY bus width is 32 bits). This field specifies which bit position the eye-scan runs on (valid range is 0 to 31). Eye-scans may be run with all possible values of ESBSEL and the results combined. Alternatively, results can be kept separate to see the effects of any duty cycle distortion / repetitive jitter.
Note: Only change this register while ESRUN=0.

8.3.9.6 ECOUNT_CLR Register (Offset = 0x1F5) [Reset = 0x00]

ECOUNT_CLR is shown in Table 8-213.

Return to the Summary Table.

Table 8-213 ECOUNT_CLR Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0
0ECOUNT_CLRR/W0x0 Program this to a 1 and then to 0 to clear the ECOUNT counters.