SBASAO8 June   2025 DAC39RF20

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI Interface Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RF Mode
        3. 7.3.1.3 DES Modes
      2. 7.3.2  DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3  DEM and Dither
      4. 7.3.4  Offset Adjustment
      5. 7.3.5  Clocking Subsystem
        1. 7.3.5.1 Converter Phase Locked Loop (CPLL)
        2. 7.3.5.2 Clock and SYSREF Delay
        3. 7.3.5.3 SYSREF Capture and Monitoring
          1. 7.3.5.3.1 SYSREF Frequency Requirements
          2. 7.3.5.3.2 SYSREF Pulses for Full Alignment
          3. 7.3.5.3.3 Automatic SYSREF Calibration and Tracking
            1. 7.3.5.3.3.1 SYSREF Automatic Calibration Procedure
            2. 7.3.5.3.3.2 Multi-device Alignment
            3. 7.3.5.3.3.3 Calibration Failure
            4. 7.3.5.3.3.4 SYSREF Tracking
        4. 7.3.5.4 Trigger Clocking
      6. 7.3.6  Digital Signal Processing Blocks
        1. 7.3.6.1  Bypass Mode
        2. 7.3.6.2  DUC Mode
          1. 7.3.6.2.1 Digital Upconverter (DUC)
            1. 7.3.6.2.1.1 Interpolation Filters
            2. 7.3.6.2.1.2 Numerically Controlled Oscillator (NCO)
              1. 7.3.6.2.1.2.1 Phase-continuous NCO Update Mode
              2. 7.3.6.2.1.2.2 Phase-coherent NCO Update Mode
              3. 7.3.6.2.1.2.3 Phase-sync NCO Update Mode
              4. 7.3.6.2.1.2.4 NCO Synchronization
                1. 7.3.6.2.1.2.4.1 JESD204C LSB Synchronization
        3. 7.3.6.3  DDS SPI Mode
        4. 7.3.6.4  DDS Vector Mode
          1. 7.3.6.4.1 Second Order Amplitude Support
          2. 7.3.6.4.2 Vector Order and Symmetric Vector Mode
          3. 7.3.6.4.3 Initial Startup
          4. 7.3.6.4.4 Trigger Queuing
          5. 7.3.6.4.5 Trigger Burst
          6. 7.3.6.4.6 Hold Mode
          7. 7.3.6.4.7 Indexing Mode
          8. 7.3.6.4.8 Queued or Burst Triggers in Indexing-Mode
          9. 7.3.6.4.9 Writing Vectors While DDS is Enabled
        5. 7.3.6.5  DDS Streaming Mode
        6. 7.3.6.6  DSP Triggering
          1. 7.3.6.6.1 Trigger Latency
        7. 7.3.6.7  NCO Square Wave Mode
          1. 7.3.6.7.1 Square Wave Enable
        8. 7.3.6.8  DSP Mute Function
        9. 7.3.6.9  DSP Output Gain
        10. 7.3.6.10 Complex Output Support
        11. 7.3.6.11 Channel Bonder
        12. 7.3.6.12 Programmable FIR Filter
          1. 7.3.6.12.1 PFIR Coefficients
          2. 7.3.6.12.2 PFIR Reflection Cancellation Mode
          3. 7.3.6.12.3 PFIR Power Savings
          4. 7.3.6.12.4 PFIR Usage
        13. 7.3.6.13 DES Interpolator
          1. 7.3.6.13.1 DAC Mute Function
      7. 7.3.7  Serdes Physical Layer
        1. 7.3.7.1 Serdes PLL
          1. 7.3.7.1.1 Enabling the Serdes PLL
          2. 7.3.7.1.2 Reference Clock
          3. 7.3.7.1.3 PLL VCO Calibration
          4. 7.3.7.1.4 Serdes PLL Loop Bandwidth
        2. 7.3.7.2 Serdes Receiver
          1. 7.3.7.2.1 Serdes Data Rate Selection
          2. 7.3.7.2.2 Serdes Receiver Termination
          3. 7.3.7.2.3 Serdes Receiver Polarity
          4. 7.3.7.2.4 Serdes Clock Data Recovery
          5. 7.3.7.2.5 Serdes Equalizer
            1. 7.3.7.2.5.1 Adaptive Equalization
            2. 7.3.7.2.5.2 Fixed Equalization
            3. 7.3.7.2.5.3 Pre and Post Cursor Analysis
          6. 7.3.7.2.6 Serdes Receiver Eyescan
            1. 7.3.7.2.6.1 Eyescan Procedure
            2. 7.3.7.2.6.2 Building an Eye Diagram
        3. 7.3.7.3 Serdes PHY Status
      8. 7.3.8  JESD204C Interface
        1. 7.3.8.1 Deviation from JESD204C Standard
        2. 7.3.8.2 Link Layer
          1. 7.3.8.2.1 Serdes Crossbar
          2. 7.3.8.2.2 Bit Error Rate Tester
          3. 7.3.8.2.3 Scrambler and Descrambler
          4. 7.3.8.2.4 64b and 66b Decoding Link Layer
            1. 7.3.8.2.4.1 Sync Header Alignment
            2. 7.3.8.2.4.2 Extended Multiblock Alignment
            3. 7.3.8.2.4.3 Data Integrity
          5. 7.3.8.2.5 8B and 10B Encoding Link Layer
            1. 7.3.8.2.5.1 Code Group Synchronization (CGS)
            2. 7.3.8.2.5.2 Initial Lane Alignment Sequence (ILAS)
            3. 7.3.8.2.5.3 Multi-frames and the Local Multiframe Clock (LMFC)
            4. 7.3.8.2.5.4 Frame and Multiframe Monitoring
            5. 7.3.8.2.5.5 Link Restart
            6. 7.3.8.2.5.6 Link Error Reports
            7. 7.3.8.2.5.7 Watchdog Timer (JTIMER)
        3. 7.3.8.3 SYSREF Alignment Required in Subclass 1 Mode
        4. 7.3.8.4 Transport Layer
        5. 7.3.8.5 JESD204C Debug Capture (JCAP)
          1. 7.3.8.5.1 Physical Layer Debug Capture
          2. 7.3.8.5.2 Link Layer Debug Capture
          3. 7.3.8.5.3 Transport Layer Debug Capture
        6. 7.3.8.6 JESD204C Interface Modes
          1. 7.3.8.6.1 JESD204C Format Diagrams
            1. 7.3.8.6.1.1 16-bit Formats
            2. 7.3.8.6.1.2 12-bit Formats
            3. 7.3.8.6.1.3 8-bit Formats
          2. 7.3.8.6.2 DUC and DDS Modes
      9. 7.3.9  Data Path Latency
      10. 7.3.10 Multi-Device Synchronization and Deterministic Latency
        1. 7.3.10.1 Programming RBD
        2. 7.3.10.2 Multiframe Lengths less than 32 Octa-Bytes (256 Bytes)
        3. 7.3.10.3 Recommended Algorithm to Determine the RBD Value
        4. 7.3.10.4 Operation in Subclass 0 Systems
      11. 7.3.11 Link Reset
      12. 7.3.12 Alarm Generation
        1. 7.3.12.1 Over Range Detection
        2. 7.3.12.2 Over Range Masking
      13. 7.3.13 Mute Function
        1. 7.3.13.1 Alarm Data Path Muting
        2. 7.3.13.2 Transmit Enables
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
  9. 8 Programming
    1. 8.1 Using the Standard SPI Interface
      1. 8.1.1 SCS
      2. 8.1.2 SCLK
      3. 8.1.3 SDI
      4. 8.1.4 SDO
      5. 8.1.5 Serial Interface Protocol
      6. 8.1.6 Streaming Mode
    2. 8.2 Using the Fast Reconfiguration Interface
    3. 8.3 Register Maps
      1. 8.3.1  Standard_SPI-3.1 Registers
      2. 8.3.2  System Registers
      3. 8.3.3  Trigger Registers
      4. 8.3.4  CPLL_AND_CLOCK Registers
      5. 8.3.5  SYSREF Registers
      6. 8.3.6  JESD204C Registers
      7. 8.3.7  JESD204C_Advanced Registers
      8. 8.3.8  SerDes_Equalizer Registers
      9. 8.3.9  SerDes_Eye-Scan Registers
      10. 8.3.10 SerDes_Lane_Status Registers
      11. 8.3.11 SerDes_PLL Registers
      12. 8.3.12 DAC_and_Analog_Configuration Registers
      13. 8.3.13 Datapath Registers
      14. 8.3.14 NCO_and_Mixer Registers
      15. 8.3.15 Alarm Registers
      16. 8.3.16 Fuse_Control Registers
      17. 8.3.17 Fuse_Backed Registers
      18. 8.3.18 DDS_Vector_Mode Registers
      19. 8.3.19 Programmable_FIR Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Startup Procedure
      2. 9.1.2 Bandwidth Optimization for Square Wave Mode
    2. 9.2 Typical Application: Ku-Band Radar Transmitter
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Up and Down Sequence
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines and Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.5 SYSREF Registers

Table 8-44 lists the memory-mapped registers for the SYSREF registers. All register offset addresses not listed in Table 8-44 should be considered as reserved locations and the register contents should not be modified.

Table 8-44 SYSREF Registers
OffsetAcronymRegister NameSection
0xA0SYSREF_ALIGNSection 8.3.5.1
0xA2SYSREF_CALTRKSection 8.3.5.2
0xA3SYSREF_RX_ENSection 8.3.5.3
0xA4SYSREF_PROC_ENSection 8.3.5.4
0xA5SRCAL_CTRLSection 8.3.5.5
0xB0TADJSection 8.3.5.6
0xB3TSYSSection 8.3.5.7
0xC0TADJ_CALSection 8.3.5.8
0xC3TSYS_CALSection 8.3.5.9
0xDESRCAL_FREEZESection 8.3.5.10
0xDFSRCAL_STATSection 8.3.5.11
0xFFSYNC_STATUSSection 8.3.5.12

Complex bit access types are encoded to fit into small table cells. Table 8-45 shows the codes that are used for access types in this section.

Table 8-45 SYSREF Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value

8.3.5.1 SYSREF_ALIGN Register (Offset = 0xA0) [Reset = 0x00]

SYSREF_ALIGN is shown in Table 8-46.

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Table 8-46 SYSREF_ALIGN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0 Reserved
0SYSREF_ALIGN_ENR/W0x0 If this bit is set, the chip realigns to each detected SYSREF edge. This affects both the external clock divider and all active internal clocks. If this bit is not set, the chip will not realign to any SYSREF edges, and the JESD204C link will not restart in response to any mis-aligned SYSREF edges.

8.3.5.2 SYSREF_CALTRK Register (Offset = 0xA2) [Reset = 0x74]

SYSREF_CALTRK is shown in Table 8-47.

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Table 8-47 SYSREF_CALTRK Register Field Descriptions
BitFieldTypeResetDescription
7-6SRCAL_AVGR/W0x1 Specifies the amount of averaging used for SYSREF Calibration. Larger values will increase calibration time and reduce the variance of the calibrated value.
  • 0x0 = 4 accumulations
  • 0x1 = 16 accumulations
  • 0x2 = 64 accumulations
  • 0x3 = 256 accumulations
5SRTRK_ENR/W0x1 When set, tracking is allowed to run once calibration completes. When cleared, tracking is not run after calibration. This can be used to disable tracking both to measure the noise impact that tracking has and to avoid tracking causing problems if it doesn 't work correctly.
4SRTRK_HYST_ENR/W0x1 When set, the low speed tracking accumulator must be within 2SRTRK_AVG+1 of its min or max value before tracking will make an adjustments. See Tracking.
3-2SRTRK_AVGR/W0x1 Specifies the amount of averaging used for SYSREF Tracking. Larger values will decrease tracking rate and increase the likelihood that tracking will fail.
  • 0x0 = 16 accumulations
  • 0x1 = 64 accumulations
  • 0x2 = 256 accumulations
  • 0x3 = 1024 accumulations
1-0SRTRK_STEPR/W0x0 Specifies the step size used for SYSREF Tracking. Larger values will increase the tracking rate and increase the likelihood that tracking will work but may also increase the delay changes that occur during tracking.
  • 0x0 = 32 LSB steps for each change
  • 0x1 = 64 LSB steps for each change
  • 0x2 = 256 LSB steps for each change
  • 0x3 = 1024 LSB steps for each change

8.3.5.3 SYSREF_RX_EN Register (Offset = 0xA3) [Reset = 0x00]

SYSREF_RX_EN is shown in Table 8-48.

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Table 8-48 SYSREF_RX_EN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0 Reserved
0SYSREF_RX_ENR/W0x0 Set this bit to enable the SYSREF receiver circuit. User should always clear SYSREF_PROC_EN before clearing this bit.
Note: This bit should only be set if CPLL_EN=0.

8.3.5.4 SYSREF_PROC_EN Register (Offset = 0xA4) [Reset = 0x00]

SYSREF_PROC_EN is shown in Table 8-49.

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Table 8-49 SYSREF_PROC_EN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0 Reserved
0SYSREF_PROC_ENR/W0x0 When set, this bit enables the SYSREF processor. When this is enabled, the system receives and processes each new SYSREF edge. User should always set SYSREF_RX_EN before setting this bit. This bit is provided to allow the SYSREF receiver to stabilize before allowing the SYSREF to come to the digital.

8.3.5.5 SRCAL_CTRL Register (Offset = 0xA5) [Reset = 0x00]

SRCAL_CTRL is shown in Table 8-50.

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Table 8-50 SRCAL_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0 Reserved
0SRCAL_ENR/W0x0 When cleared, the internal SYSREF calibration and tracking engine is reset and SYSREF_CAL_DONE is cleared. Setting this bit allows SYSREF calibration and tracking to run.

8.3.5.6 TADJ Register (Offset = 0xB0) [Reset = 0x000000]

TADJ is shown in Table 8-51.

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Table 8-51 TADJ Register Field Descriptions
BitFieldTypeResetDescription
23CALCLK_INVR/W0x0 When set, inverts the clock input.
Note: This register is only used when SRCAL_EN=0.
22-19RESERVEDR0x0 Reserved
18-0TADJR/W0x0 This defines the DEVCLK delay adjustment when SYSREF calibration is disabled (SRCAL_EN=0). See Timing Adjust Blocks for encoding description.
Note: This register is only used when SRCAL_EN=0.

8.3.5.7 TSYS Register (Offset = 0xB3) [Reset = 0x040000]

TSYS is shown in Table 8-52.

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Table 8-52 TSYS Register Field Descriptions
BitFieldTypeResetDescription
23-19RESERVEDR0x0 Reserved
18-0TSYSR/W0x00040000 This defines the SYSREF delay adjustment when SYSREF tracking is disabled (SRCAL_EN=0 or SRTRK_EN=0). See Timing Adjust Blocks for encoding description.
Note: Note: This register should only be changed when SRCAL_EN=0 or SRTRK_EN=0.

8.3.5.8 TADJ_CAL Register (Offset = 0xC0) [Reset = 0xXXXXXX]

TADJ_CAL is shown in Table 8-53.

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Table 8-53 TADJ_CAL Register Field Descriptions
BitFieldTypeResetDescription
23CALCLK_INV_CALRX This register field should be the clock inversion calibration value, but due to a bug always returns zero. CALCLK_INV is working in the calibration routine.
22-19RESERVEDR0x0 Reserved
18-0TADJ_CALRX This returns a snapshot of the CLK delay adjustment produced by SYSREF calibration..
Note: This register is is only valid when SRCAL_EN=1.
Note: This register should only be read when SRCAL_FREEZE=1 or SYSREF_CAL_DONE=1.

8.3.5.9 TSYS_CAL Register (Offset = 0xC3) [Reset = 0x0XXXXX]

TSYS_CAL is shown in Table 8-54.

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Table 8-54 TSYS_CAL Register Field Descriptions
BitFieldTypeResetDescription
23-19RESERVEDR0x0 Reserved
18-0TSYS_CALRX This returns a snapshot of the SYSREF delay adjustment produced by SYSREF tracking.
Note: This register is only valid when SRCAL_EN=1 and SRTRK_EN=1.
Note: This register should only be read when SRCAL_FREEZE=1.

8.3.5.10 SRCAL_FREEZE Register (Offset = 0xDE) [Reset = 0x00]

SRCAL_FREEZE is shown in Table 8-55.

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Table 8-55 SRCAL_FREEZE Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0 Reserved
0SRCAL_FREEZER/W0x0 When set, the TADJ_CAL and TSYS_CAL will freeze at their current values so they can be read. The calibration and tracking algorithm will continue to operate.
User must wait at least 24 SYSREF periods after setting this bit before attempting to read TADJ_CAL or TSYS_CAL. When clearing this bit, it must remain low for more than 8 SYSREF periods to ensure data will be updated.
This register is only useful when SRCAL_EN=1.
Note: The frozen values of TADJ_CAL and TSYS_CAL are not upset immune.

8.3.5.11 SRCAL_STAT Register (Offset = 0xDF) [Reset = 0x0X]

SRCAL_STAT is shown in Table 8-56.

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Table 8-56 SRCAL_STAT Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0 Reserved
3SYSREF_ALIGNMENTRX When this value is high, the clock is high when SYSREF rises.The value returned here is an averaged over 8*SRCAL_AVG cycles. When the CPLL is in use, the DEVCLK SYSREF samplers are used. Otherwise, the DACCLK SYSREF samples are used.
Note: The value in this register is undefined when SYSREF_WIN_EN=1.
2SYSREF_CAL_FAILRX Set if the SYSREF calibration process fails to find alignment. This bit is cleared any time (SYSREF_RX_EN = 0 AND SRCAL_EN = 0.
1SYSREF_TRACK_FAILRX Set if SYSREF tracking runs out of delay range while tracking the window. Tracking attempts to continue running when this occurs but it may not be able to maintain the SYSREF sampling window. The user should rerun calibration when this occurs. This bit is cleared any time SYSREF_RX_EN = 0 and SRCAL_EN = 0.
0SYSREF_CAL_DONERX Set when SYSREF calibration completes successfully. This bit is cleared any time SYSREF_RX_EN = 0 and SRCAL_EN = 0.

8.3.5.12 SYNC_STATUS Register (Offset = 0xFF) [Reset = 0xXX]

SYNC_STATUS is shown in Table 8-57.

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Table 8-57 SYNC_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0x0
4DIV_REALIGNEDR/W1CX This bit is set any time the divide-by-16 clock divider is realigned to SYSREF. This bit is primarily for debug purposes as CLK_REALIGNED is more appropriate for customer use. Write a 1 to clear this bit.
3CLK_REALIGNEDR/W1CX This bit is set any time an active SYSREF-associated clock divider is realigned to a SYSREF edge. This bit is useful to confirm the internally sampled SYSREF signal has a correct and stable period. Write a 1 to clear this bit.
2CLK_ALIGNEDRX Indicates if the last SYSREF pulse was consistent with all active SYSREF-associated clock dividers (and the dividers required no adjustment) (1=consistent, 0=not consistent). The part may require up to two SYSREF pulses (both consistent with the clock dividers) to set this bit. This bit is read-only (cannot be cleared via SPI). This bit reports alignment status regardless of the state of SYSREF_ALIGN_EN.
1RESERVEDR0x0
0SYSREF_DETR/W1CX This bit is set when a SYSREF is detected. Write a 1 to clear the bit and allow it to be re-detected.