SBASAO8 June   2025 DAC39RF20

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI Interface Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RF Mode
        3. 7.3.1.3 DES Modes
      2. 7.3.2  DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3  DEM and Dither
      4. 7.3.4  Offset Adjustment
      5. 7.3.5  Clocking Subsystem
        1. 7.3.5.1 Converter Phase Locked Loop (CPLL)
        2. 7.3.5.2 Clock and SYSREF Delay
        3. 7.3.5.3 SYSREF Capture and Monitoring
          1. 7.3.5.3.1 SYSREF Frequency Requirements
          2. 7.3.5.3.2 SYSREF Pulses for Full Alignment
          3. 7.3.5.3.3 Automatic SYSREF Calibration and Tracking
            1. 7.3.5.3.3.1 SYSREF Automatic Calibration Procedure
            2. 7.3.5.3.3.2 Multi-device Alignment
            3. 7.3.5.3.3.3 Calibration Failure
            4. 7.3.5.3.3.4 SYSREF Tracking
        4. 7.3.5.4 Trigger Clocking
      6. 7.3.6  Digital Signal Processing Blocks
        1. 7.3.6.1  Bypass Mode
        2. 7.3.6.2  DUC Mode
          1. 7.3.6.2.1 Digital Upconverter (DUC)
            1. 7.3.6.2.1.1 Interpolation Filters
            2. 7.3.6.2.1.2 Numerically Controlled Oscillator (NCO)
              1. 7.3.6.2.1.2.1 Phase-continuous NCO Update Mode
              2. 7.3.6.2.1.2.2 Phase-coherent NCO Update Mode
              3. 7.3.6.2.1.2.3 Phase-sync NCO Update Mode
              4. 7.3.6.2.1.2.4 NCO Synchronization
                1. 7.3.6.2.1.2.4.1 JESD204C LSB Synchronization
        3. 7.3.6.3  DDS SPI Mode
        4. 7.3.6.4  DDS Vector Mode
          1. 7.3.6.4.1 Second Order Amplitude Support
          2. 7.3.6.4.2 Vector Order and Symmetric Vector Mode
          3. 7.3.6.4.3 Initial Startup
          4. 7.3.6.4.4 Trigger Queuing
          5. 7.3.6.4.5 Trigger Burst
          6. 7.3.6.4.6 Hold Mode
          7. 7.3.6.4.7 Indexing Mode
          8. 7.3.6.4.8 Queued or Burst Triggers in Indexing-Mode
          9. 7.3.6.4.9 Writing Vectors While DDS is Enabled
        5. 7.3.6.5  DDS Streaming Mode
        6. 7.3.6.6  DSP Triggering
          1. 7.3.6.6.1 Trigger Latency
        7. 7.3.6.7  NCO Square Wave Mode
          1. 7.3.6.7.1 Square Wave Enable
        8. 7.3.6.8  DSP Mute Function
        9. 7.3.6.9  DSP Output Gain
        10. 7.3.6.10 Complex Output Support
        11. 7.3.6.11 Channel Bonder
        12. 7.3.6.12 Programmable FIR Filter
          1. 7.3.6.12.1 PFIR Coefficients
          2. 7.3.6.12.2 PFIR Reflection Cancellation Mode
          3. 7.3.6.12.3 PFIR Power Savings
          4. 7.3.6.12.4 PFIR Usage
        13. 7.3.6.13 DES Interpolator
          1. 7.3.6.13.1 DAC Mute Function
      7. 7.3.7  Serdes Physical Layer
        1. 7.3.7.1 Serdes PLL
          1. 7.3.7.1.1 Enabling the Serdes PLL
          2. 7.3.7.1.2 Reference Clock
          3. 7.3.7.1.3 PLL VCO Calibration
          4. 7.3.7.1.4 Serdes PLL Loop Bandwidth
        2. 7.3.7.2 Serdes Receiver
          1. 7.3.7.2.1 Serdes Data Rate Selection
          2. 7.3.7.2.2 Serdes Receiver Termination
          3. 7.3.7.2.3 Serdes Receiver Polarity
          4. 7.3.7.2.4 Serdes Clock Data Recovery
          5. 7.3.7.2.5 Serdes Equalizer
            1. 7.3.7.2.5.1 Adaptive Equalization
            2. 7.3.7.2.5.2 Fixed Equalization
            3. 7.3.7.2.5.3 Pre and Post Cursor Analysis
          6. 7.3.7.2.6 Serdes Receiver Eyescan
            1. 7.3.7.2.6.1 Eyescan Procedure
            2. 7.3.7.2.6.2 Building an Eye Diagram
        3. 7.3.7.3 Serdes PHY Status
      8. 7.3.8  JESD204C Interface
        1. 7.3.8.1 Deviation from JESD204C Standard
        2. 7.3.8.2 Link Layer
          1. 7.3.8.2.1 Serdes Crossbar
          2. 7.3.8.2.2 Bit Error Rate Tester
          3. 7.3.8.2.3 Scrambler and Descrambler
          4. 7.3.8.2.4 64b and 66b Decoding Link Layer
            1. 7.3.8.2.4.1 Sync Header Alignment
            2. 7.3.8.2.4.2 Extended Multiblock Alignment
            3. 7.3.8.2.4.3 Data Integrity
          5. 7.3.8.2.5 8B and 10B Encoding Link Layer
            1. 7.3.8.2.5.1 Code Group Synchronization (CGS)
            2. 7.3.8.2.5.2 Initial Lane Alignment Sequence (ILAS)
            3. 7.3.8.2.5.3 Multi-frames and the Local Multiframe Clock (LMFC)
            4. 7.3.8.2.5.4 Frame and Multiframe Monitoring
            5. 7.3.8.2.5.5 Link Restart
            6. 7.3.8.2.5.6 Link Error Reports
            7. 7.3.8.2.5.7 Watchdog Timer (JTIMER)
        3. 7.3.8.3 SYSREF Alignment Required in Subclass 1 Mode
        4. 7.3.8.4 Transport Layer
        5. 7.3.8.5 JESD204C Debug Capture (JCAP)
          1. 7.3.8.5.1 Physical Layer Debug Capture
          2. 7.3.8.5.2 Link Layer Debug Capture
          3. 7.3.8.5.3 Transport Layer Debug Capture
        6. 7.3.8.6 JESD204C Interface Modes
          1. 7.3.8.6.1 JESD204C Format Diagrams
            1. 7.3.8.6.1.1 16-bit Formats
            2. 7.3.8.6.1.2 12-bit Formats
            3. 7.3.8.6.1.3 8-bit Formats
          2. 7.3.8.6.2 DUC and DDS Modes
      9. 7.3.9  Data Path Latency
      10. 7.3.10 Multi-Device Synchronization and Deterministic Latency
        1. 7.3.10.1 Programming RBD
        2. 7.3.10.2 Multiframe Lengths less than 32 Octa-Bytes (256 Bytes)
        3. 7.3.10.3 Recommended Algorithm to Determine the RBD Value
        4. 7.3.10.4 Operation in Subclass 0 Systems
      11. 7.3.11 Link Reset
      12. 7.3.12 Alarm Generation
        1. 7.3.12.1 Over Range Detection
        2. 7.3.12.2 Over Range Masking
      13. 7.3.13 Mute Function
        1. 7.3.13.1 Alarm Data Path Muting
        2. 7.3.13.2 Transmit Enables
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
  9. 8 Programming
    1. 8.1 Using the Standard SPI Interface
      1. 8.1.1 SCS
      2. 8.1.2 SCLK
      3. 8.1.3 SDI
      4. 8.1.4 SDO
      5. 8.1.5 Serial Interface Protocol
      6. 8.1.6 Streaming Mode
    2. 8.2 Using the Fast Reconfiguration Interface
    3. 8.3 Register Maps
      1. 8.3.1  Standard_SPI-3.1 Registers
      2. 8.3.2  System Registers
      3. 8.3.3  Trigger Registers
      4. 8.3.4  CPLL_AND_CLOCK Registers
      5. 8.3.5  SYSREF Registers
      6. 8.3.6  JESD204C Registers
      7. 8.3.7  JESD204C_Advanced Registers
      8. 8.3.8  SerDes_Equalizer Registers
      9. 8.3.9  SerDes_Eye-Scan Registers
      10. 8.3.10 SerDes_Lane_Status Registers
      11. 8.3.11 SerDes_PLL Registers
      12. 8.3.12 DAC_and_Analog_Configuration Registers
      13. 8.3.13 Datapath Registers
      14. 8.3.14 NCO_and_Mixer Registers
      15. 8.3.15 Alarm Registers
      16. 8.3.16 Fuse_Control Registers
      17. 8.3.17 Fuse_Backed Registers
      18. 8.3.18 DDS_Vector_Mode Registers
      19. 8.3.19 Programmable_FIR Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Startup Procedure
      2. 9.1.2 Bandwidth Optimization for Square Wave Mode
    2. 9.2 Typical Application: Ku-Band Radar Transmitter
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Up and Down Sequence
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines and Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.8 SerDes_Equalizer Registers

Table 8-184 lists the memory-mapped registers for the SerDes_Equalizer registers. All register offset addresses not listed in Table 8-184 should be considered as reserved locations and the register contents should not be modified.

Table 8-184 SERDES_EQUALIZER Registers
OffsetAcronymRegister NameSection
0x1C0CDR0Section 8.3.8.1
0x1D0EQ_CTRLSection 8.3.8.2
0x1D1EQZEROSection 8.3.8.3
0x1D2LANE_EQ_0Section 8.3.8.4
0x1D3LANE_EQ_1Section 8.3.8.5
0x1D4LANE_EQ_2Section 8.3.8.6
0x1D5LANE_EQ_3Section 8.3.8.7
0x1D6LANE_EQ_4Section 8.3.8.8
0x1D7LANE_EQ_5Section 8.3.8.9
0x1D8LANE_EQ_6Section 8.3.8.10
0x1D9LANE_EQ_7Section 8.3.8.11
0x1DALANE_EQ_8Section 8.3.8.12
0x1DBLANE_EQ_9Section 8.3.8.13
0x1DCLANE_EQ_10Section 8.3.8.14
0x1DDLANE_EQ_11Section 8.3.8.15
0x1DELANE_EQ_12Section 8.3.8.16
0x1DFLANE_EQ_13Section 8.3.8.17
0x1E0LANE_EQ_14Section 8.3.8.18
0x1E1LANE_EQ_15Section 8.3.8.19
0x1E2EQDEBUGSection 8.3.8.20

Complex bit access types are encoded to fit into small table cells. Table 8-185 shows the codes that are used for access types in this section.

Table 8-185 SerDes_Equalizer Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.3.8.1 CDR0 Register (Offset = 0x1C0) [Reset = 0x51]

CDR0 is shown in Table 8-186.

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Table 8-186 CDR0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0
6-4CDRVOTER/W0x5 Specifies how many (net) votes are needed to cause the CDR loop to adjust the phase interpolators. Higher settings slow down the loop, but decrease loop noise.
Note: This register should only be changed when SYS_EN=0.
  • 0x0 = 1
  • 0x1 = 3
  • 0x2 = 5
  • 0x3 = 7
  • 0x4 = 15
  • 0x5 = 31 (default)
  • 0x6 = Reserved
  • 0x7 = Reserved
3-2RESERVEDR0x0
1-0CDRSTLR/W0x1 Specifies how long the CDR loop stops analyzing data after each adjustment to the phase interpolators.
Note: This register should only be changed when SYS_EN=0.
  • 0x0 = 32UI
  • 0x1 = 96UI
  • 0x2 = 192UI
  • 0x3 = 2016UI

8.3.8.2 EQ_CTRL Register (Offset = 0x1D0) [Reset = 0x00]

EQ_CTRL is shown in Table 8-187.

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Table 8-187 EQ_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0x0
4EQ_OVRR/W0x0 When EQMODE is 1 or higher, you can program EQ_OVR=1 to over-ride the equalizer level using the EQLEVEL[n] registers. Affects all lanes.
3EQZ_OVRR/W0x0 Set this bit to enable the EQZERO register (to override the equalizer's zero frequency). When EQZ_OVR=0, the frequency is set based on the RATE register. Affects all lanes.
2EQHOLDR/W0x0 When the equalizer is in fully-adaptive mode (EQMODE=1 and EQ_OVR=0), programming EQHOLD will freeze (hold) the adaptation loop (for all lanes).
1-0EQMODER/W0x0 Sets the equalizer mode (for all lanes): See Equalizer section.
  • 0x0 = EQ_DISABLE
  • 0x1 = EQ_ENABLE
  • 0x2 = EQ_PRECURSOR
  • 0x3 = EQ_POSTCURSOR

8.3.8.3 EQZERO Register (Offset = 0x1D1) [Reset = 0x00]

EQZERO is shown in Table 8-188.

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Table 8-188 EQZERO Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0x0
4-0EQZEROR/W0x0 When EQZ_OVR=1, this field over-rides the equalizers zero frequency (for all lanes). When EQZ_OVR=0, the zero frequency is set automatically based on the RATE setting.
EQZERO:Zero Frequency (MHz):Notes
0:114:
2:124:Automatic setting for RATE = 4
10:169:
17:222:Automatic setting for RATE = 3
22:326:
25:426:Automatic setting for RATE = 2
27:615:
29:792:Automatic setting for RATE = 1
30:1122:
31:2027::Automatic setting for RATE = 0
all others:RESERVED:

8.3.8.4 LANE_EQ_0 Register (Offset = 0x1D2) [Reset = 0x17]

LANE_EQ_0 is shown in Table 8-189.

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Table 8-189 LANE_EQ_0 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0
5-4EQTRIM[0]R/W0x1 Controls EQ trim for physical lane 0.
  • 0x0 = EQ_TRIM_POS12
  • 0x1 = EQ_TRIM_DEFAULT
  • 0x2 = EQ_TRIM_NEG10
  • 0x3 = EQ_TRIM_NEG18
3-0EQLEVEL[0]R/W0x7 When EQ_OVR=1, this field controls the equalization level for physical lane 0. The valid range is from 0 to 14.

8.3.8.5 LANE_EQ_1 Register (Offset = 0x1D3) [Reset = 0x17]

LANE_EQ_1 is shown in Table 8-190.

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Table 8-190 LANE_EQ_1 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0
5-4EQTRIM[1]R/W0x1 Controls EQ trim for physical lane 1.
  • 0x0 = EQ_TRIM_POS12
  • 0x1 = EQ_TRIM_DEFAULT
  • 0x2 = EQ_TRIM_NEG10
  • 0x3 = EQ_TRIM_NEG18
3-0EQLEVEL[1]R/W0x7 When EQ_OVR=1, this field controls the equalization level for physical lane 1. The valid range is from 0 to 14.

8.3.8.6 LANE_EQ_2 Register (Offset = 0x1D4) [Reset = 0x17]

LANE_EQ_2 is shown in Table 8-191.

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Table 8-191 LANE_EQ_2 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0
5-4EQTRIM[2]R/W0x1 Controls EQ trim for physical lane 2.
  • 0x0 = EQ_TRIM_POS12
  • 0x1 = EQ_TRIM_DEFAULT
  • 0x2 = EQ_TRIM_NEG10
  • 0x3 = EQ_TRIM_NEG18
3-0EQLEVEL[2]R/W0x7 When EQ_OVR=1, this field controls the equalization level for physical lane 2. The valid range is from 0 to 14.

8.3.8.7 LANE_EQ_3 Register (Offset = 0x1D5) [Reset = 0x17]

LANE_EQ_3 is shown in Table 8-192.

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Table 8-192 LANE_EQ_3 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0
5-4EQTRIM[3]R/W0x1 Controls EQ trim for physical lane 3.
  • 0x0 = EQ_TRIM_POS12
  • 0x1 = EQ_TRIM_DEFAULT
  • 0x2 = EQ_TRIM_NEG10
  • 0x3 = EQ_TRIM_NEG18
3-0EQLEVEL[3]R/W0x7 When EQ_OVR=1, this field controls the equalization level for physical lane 3. The valid range is from 0 to 14.

8.3.8.8 LANE_EQ_4 Register (Offset = 0x1D6) [Reset = 0x17]

LANE_EQ_4 is shown in Table 8-193.

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Table 8-193 LANE_EQ_4 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0
5-4EQTRIM[4]R/W0x1 Controls EQ trim for physical lane 4.
  • 0x0 = EQ_TRIM_POS12
  • 0x1 = EQ_TRIM_DEFAULT
  • 0x2 = EQ_TRIM_NEG10
  • 0x3 = EQ_TRIM_NEG18
3-0EQLEVEL[4]R/W0x7 When EQ_OVR=1, this field controls the equalization level for physical lane 4. The valid range is from 0 to 14.

8.3.8.9 LANE_EQ_5 Register (Offset = 0x1D7) [Reset = 0x17]

LANE_EQ_5 is shown in Table 8-194.

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Table 8-194 LANE_EQ_5 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0
5-4EQTRIM[5]R/W0x1 Controls EQ trim for physical lane 5.
  • 0x0 = EQ_TRIM_POS12
  • 0x1 = EQ_TRIM_DEFAULT
  • 0x2 = EQ_TRIM_NEG10
  • 0x3 = EQ_TRIM_NEG18
3-0EQLEVEL[5]R/W0x7 When EQ_OVR=1, this field controls the equalization level for physical lane 5. The valid range is from 0 to 14.

8.3.8.10 LANE_EQ_6 Register (Offset = 0x1D8) [Reset = 0x17]

LANE_EQ_6 is shown in Table 8-195.

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Table 8-195 LANE_EQ_6 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0
5-4EQTRIM[6]R/W0x1 Controls EQ trim for physical lane 6.
  • 0x0 = EQ_TRIM_POS12
  • 0x1 = EQ_TRIM_DEFAULT
  • 0x2 = EQ_TRIM_NEG10
  • 0x3 = EQ_TRIM_NEG18
3-0EQLEVEL[6]R/W0x7 When EQ_OVR=1, this field controls the equalization level for physical lane 6. The valid range is from 0 to 14.

8.3.8.11 LANE_EQ_7 Register (Offset = 0x1D9) [Reset = 0x17]

LANE_EQ_7 is shown in Table 8-196.

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Table 8-196 LANE_EQ_7 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0
5-4EQTRIM[7]R/W0x1 Controls EQ trim for physical lane 7.
  • 0x0 = EQ_TRIM_POS12
  • 0x1 = EQ_TRIM_DEFAULT
  • 0x2 = EQ_TRIM_NEG10
  • 0x3 = EQ_TRIM_NEG18
3-0EQLEVEL[7]R/W0x7 When EQ_OVR=1, this field controls the equalization level for physical lane 7. The valid range is from 0 to 14.

8.3.8.12 LANE_EQ_8 Register (Offset = 0x1DA) [Reset = 0x17]

LANE_EQ_8 is shown in Table 8-197.

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Table 8-197 LANE_EQ_8 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0
5-4EQTRIM[8]R/W0x1 Controls EQ trim for physical lane 8.
  • 0x0 = EQ_TRIM_POS12
  • 0x1 = EQ_TRIM_DEFAULT
  • 0x2 = EQ_TRIM_NEG10
  • 0x3 = EQ_TRIM_NEG18
3-0EQLEVEL[8]R/W0x7 When EQ_OVR=1, this field controls the equalization level for physical lane 8. The valid range is from 0 to 14.

8.3.8.13 LANE_EQ_9 Register (Offset = 0x1DB) [Reset = 0x17]

LANE_EQ_9 is shown in Table 8-198.

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Table 8-198 LANE_EQ_9 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0
5-4EQTRIM[9]R/W0x1 Controls EQ trim for physical lane 9.
  • 0x0 = EQ_TRIM_POS12
  • 0x1 = EQ_TRIM_DEFAULT
  • 0x2 = EQ_TRIM_NEG10
  • 0x3 = EQ_TRIM_NEG18
3-0EQLEVEL[9]R/W0x7 When EQ_OVR=1, this field controls the equalization level for physical lane 9. The valid range is from 0 to 14.

8.3.8.14 LANE_EQ_10 Register (Offset = 0x1DC) [Reset = 0x17]

LANE_EQ_10 is shown in Table 8-199.

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Table 8-199 LANE_EQ_10 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0
5-4EQTRIM[10]R/W0x1 Controls EQ trim for physical lane 10.
  • 0x0 = EQ_TRIM_POS12
  • 0x1 = EQ_TRIM_DEFAULT
  • 0x2 = EQ_TRIM_NEG10
  • 0x3 = EQ_TRIM_NEG18
3-0EQLEVEL[10]R/W0x7 When EQ_OVR=1, this field controls the equalization level for physical lane 10. The valid range is from 0 to 14.

8.3.8.15 LANE_EQ_11 Register (Offset = 0x1DD) [Reset = 0x17]

LANE_EQ_11 is shown in Table 8-200.

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Table 8-200 LANE_EQ_11 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0
5-4EQTRIM[11]R/W0x1 Controls EQ trim for physical lane 11.
  • 0x0 = EQ_TRIM_POS12
  • 0x1 = EQ_TRIM_DEFAULT
  • 0x2 = EQ_TRIM_NEG10
  • 0x3 = EQ_TRIM_NEG18
3-0EQLEVEL[11]R/W0x7 When EQ_OVR=1, this field controls the equalization level for physical lane 11. The valid range is from 0 to 14.

8.3.8.16 LANE_EQ_12 Register (Offset = 0x1DE) [Reset = 0x17]

LANE_EQ_12 is shown in Table 8-201.

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Table 8-201 LANE_EQ_12 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0
5-4EQTRIM[12]R/W0x1 Controls EQ trim for physical lane 12.
  • 0x0 = EQ_TRIM_POS12
  • 0x1 = EQ_TRIM_DEFAULT
  • 0x2 = EQ_TRIM_NEG10
  • 0x3 = EQ_TRIM_NEG18
3-0EQLEVEL[12]R/W0x7 When EQ_OVR=1, this field controls the equalization level for physical lane 12. The valid range is from 0 to 14.

8.3.8.17 LANE_EQ_13 Register (Offset = 0x1DF) [Reset = 0x17]

LANE_EQ_13 is shown in Table 8-202.

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Table 8-202 LANE_EQ_13 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0
5-4EQTRIM[13]R/W0x1 Controls EQ trim for physical lane 13.
  • 0x0 = EQ_TRIM_POS12
  • 0x1 = EQ_TRIM_DEFAULT
  • 0x2 = EQ_TRIM_NEG10
  • 0x3 = EQ_TRIM_NEG18
3-0EQLEVEL[13]R/W0x7 When EQ_OVR=1, this field controls the equalization level for physical lane 13. The valid range is from 0 to 14.

8.3.8.18 LANE_EQ_14 Register (Offset = 0x1E0) [Reset = 0x17]

LANE_EQ_14 is shown in Table 8-203.

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Table 8-203 LANE_EQ_14 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0
5-4EQTRIM[14]R/W0x1 Controls EQ trim for physical lane 14.
  • 0x0 = EQ_TRIM_POS12
  • 0x1 = EQ_TRIM_DEFAULT
  • 0x2 = EQ_TRIM_NEG10
  • 0x3 = EQ_TRIM_NEG18
3-0EQLEVEL[14]R/W0x7 When EQ_OVR=1, this field controls the equalization level for physical lane 14. The valid range is from 0 to 14.

8.3.8.19 LANE_EQ_15 Register (Offset = 0x1E1) [Reset = 0x17]

LANE_EQ_15 is shown in Table 8-204.

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Table 8-204 LANE_EQ_15 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0
5-4EQTRIM[15]R/W0x1 Controls EQ trim for physical lane 15.
  • 0x0 = EQ_TRIM_POS12
  • 0x1 = EQ_TRIM_DEFAULT
  • 0x2 = EQ_TRIM_NEG10
  • 0x3 = EQ_TRIM_NEG18
3-0EQLEVEL[15]R/W0x7 When EQ_OVR=1, this field controls the equalization level for physical lane 15. The valid range is from 0 to 14.

8.3.8.20 EQDEBUG Register (Offset = 0x1E2) [Reset = 0x06]

EQDEBUG is shown in Table 8-205.

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Table 8-205 EQDEBUG Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0
5EQUDR/W0x0 When set, the adaptive EQ will detect "P" patterns to improve its ability to recover from severely under-equalized situations that may prevent the CDR from locking.
4EQODR/W0x0 When set, the adaptive EQ will reduce the equalization level if no equalization patterns can be detected for a long time. This helps recover from severely over-equalized situations. This feature is NOT implemented in the PHY.
3-0RESERVEDR0x0