SBASAO8 June   2025 DAC39RF20

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI Interface Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RF Mode
        3. 7.3.1.3 DES Modes
      2. 7.3.2  DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3  DEM and Dither
      4. 7.3.4  Offset Adjustment
      5. 7.3.5  Clocking Subsystem
        1. 7.3.5.1 Converter Phase Locked Loop (CPLL)
        2. 7.3.5.2 Clock and SYSREF Delay
        3. 7.3.5.3 SYSREF Capture and Monitoring
          1. 7.3.5.3.1 SYSREF Frequency Requirements
          2. 7.3.5.3.2 SYSREF Pulses for Full Alignment
          3. 7.3.5.3.3 Automatic SYSREF Calibration and Tracking
            1. 7.3.5.3.3.1 SYSREF Automatic Calibration Procedure
            2. 7.3.5.3.3.2 Multi-device Alignment
            3. 7.3.5.3.3.3 Calibration Failure
            4. 7.3.5.3.3.4 SYSREF Tracking
        4. 7.3.5.4 Trigger Clocking
      6. 7.3.6  Digital Signal Processing Blocks
        1. 7.3.6.1  Bypass Mode
        2. 7.3.6.2  DUC Mode
          1. 7.3.6.2.1 Digital Upconverter (DUC)
            1. 7.3.6.2.1.1 Interpolation Filters
            2. 7.3.6.2.1.2 Numerically Controlled Oscillator (NCO)
              1. 7.3.6.2.1.2.1 Phase-continuous NCO Update Mode
              2. 7.3.6.2.1.2.2 Phase-coherent NCO Update Mode
              3. 7.3.6.2.1.2.3 Phase-sync NCO Update Mode
              4. 7.3.6.2.1.2.4 NCO Synchronization
                1. 7.3.6.2.1.2.4.1 JESD204C LSB Synchronization
        3. 7.3.6.3  DDS SPI Mode
        4. 7.3.6.4  DDS Vector Mode
          1. 7.3.6.4.1 Second Order Amplitude Support
          2. 7.3.6.4.2 Vector Order and Symmetric Vector Mode
          3. 7.3.6.4.3 Initial Startup
          4. 7.3.6.4.4 Trigger Queuing
          5. 7.3.6.4.5 Trigger Burst
          6. 7.3.6.4.6 Hold Mode
          7. 7.3.6.4.7 Indexing Mode
          8. 7.3.6.4.8 Queued or Burst Triggers in Indexing-Mode
          9. 7.3.6.4.9 Writing Vectors While DDS is Enabled
        5. 7.3.6.5  DDS Streaming Mode
        6. 7.3.6.6  DSP Triggering
          1. 7.3.6.6.1 Trigger Latency
        7. 7.3.6.7  NCO Square Wave Mode
          1. 7.3.6.7.1 Square Wave Enable
        8. 7.3.6.8  DSP Mute Function
        9. 7.3.6.9  DSP Output Gain
        10. 7.3.6.10 Complex Output Support
        11. 7.3.6.11 Channel Bonder
        12. 7.3.6.12 Programmable FIR Filter
          1. 7.3.6.12.1 PFIR Coefficients
          2. 7.3.6.12.2 PFIR Reflection Cancellation Mode
          3. 7.3.6.12.3 PFIR Power Savings
          4. 7.3.6.12.4 PFIR Usage
        13. 7.3.6.13 DES Interpolator
          1. 7.3.6.13.1 DAC Mute Function
      7. 7.3.7  Serdes Physical Layer
        1. 7.3.7.1 Serdes PLL
          1. 7.3.7.1.1 Enabling the Serdes PLL
          2. 7.3.7.1.2 Reference Clock
          3. 7.3.7.1.3 PLL VCO Calibration
          4. 7.3.7.1.4 Serdes PLL Loop Bandwidth
        2. 7.3.7.2 Serdes Receiver
          1. 7.3.7.2.1 Serdes Data Rate Selection
          2. 7.3.7.2.2 Serdes Receiver Termination
          3. 7.3.7.2.3 Serdes Receiver Polarity
          4. 7.3.7.2.4 Serdes Clock Data Recovery
          5. 7.3.7.2.5 Serdes Equalizer
            1. 7.3.7.2.5.1 Adaptive Equalization
            2. 7.3.7.2.5.2 Fixed Equalization
            3. 7.3.7.2.5.3 Pre and Post Cursor Analysis
          6. 7.3.7.2.6 Serdes Receiver Eyescan
            1. 7.3.7.2.6.1 Eyescan Procedure
            2. 7.3.7.2.6.2 Building an Eye Diagram
        3. 7.3.7.3 Serdes PHY Status
      8. 7.3.8  JESD204C Interface
        1. 7.3.8.1 Deviation from JESD204C Standard
        2. 7.3.8.2 Link Layer
          1. 7.3.8.2.1 Serdes Crossbar
          2. 7.3.8.2.2 Bit Error Rate Tester
          3. 7.3.8.2.3 Scrambler and Descrambler
          4. 7.3.8.2.4 64b and 66b Decoding Link Layer
            1. 7.3.8.2.4.1 Sync Header Alignment
            2. 7.3.8.2.4.2 Extended Multiblock Alignment
            3. 7.3.8.2.4.3 Data Integrity
          5. 7.3.8.2.5 8B and 10B Encoding Link Layer
            1. 7.3.8.2.5.1 Code Group Synchronization (CGS)
            2. 7.3.8.2.5.2 Initial Lane Alignment Sequence (ILAS)
            3. 7.3.8.2.5.3 Multi-frames and the Local Multiframe Clock (LMFC)
            4. 7.3.8.2.5.4 Frame and Multiframe Monitoring
            5. 7.3.8.2.5.5 Link Restart
            6. 7.3.8.2.5.6 Link Error Reports
            7. 7.3.8.2.5.7 Watchdog Timer (JTIMER)
        3. 7.3.8.3 SYSREF Alignment Required in Subclass 1 Mode
        4. 7.3.8.4 Transport Layer
        5. 7.3.8.5 JESD204C Debug Capture (JCAP)
          1. 7.3.8.5.1 Physical Layer Debug Capture
          2. 7.3.8.5.2 Link Layer Debug Capture
          3. 7.3.8.5.3 Transport Layer Debug Capture
        6. 7.3.8.6 JESD204C Interface Modes
          1. 7.3.8.6.1 JESD204C Format Diagrams
            1. 7.3.8.6.1.1 16-bit Formats
            2. 7.3.8.6.1.2 12-bit Formats
            3. 7.3.8.6.1.3 8-bit Formats
          2. 7.3.8.6.2 DUC and DDS Modes
      9. 7.3.9  Data Path Latency
      10. 7.3.10 Multi-Device Synchronization and Deterministic Latency
        1. 7.3.10.1 Programming RBD
        2. 7.3.10.2 Multiframe Lengths less than 32 Octa-Bytes (256 Bytes)
        3. 7.3.10.3 Recommended Algorithm to Determine the RBD Value
        4. 7.3.10.4 Operation in Subclass 0 Systems
      11. 7.3.11 Link Reset
      12. 7.3.12 Alarm Generation
        1. 7.3.12.1 Over Range Detection
        2. 7.3.12.2 Over Range Masking
      13. 7.3.13 Mute Function
        1. 7.3.13.1 Alarm Data Path Muting
        2. 7.3.13.2 Transmit Enables
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
  9. 8 Programming
    1. 8.1 Using the Standard SPI Interface
      1. 8.1.1 SCS
      2. 8.1.2 SCLK
      3. 8.1.3 SDI
      4. 8.1.4 SDO
      5. 8.1.5 Serial Interface Protocol
      6. 8.1.6 Streaming Mode
    2. 8.2 Using the Fast Reconfiguration Interface
    3. 8.3 Register Maps
      1. 8.3.1  Standard_SPI-3.1 Registers
      2. 8.3.2  System Registers
      3. 8.3.3  Trigger Registers
      4. 8.3.4  CPLL_AND_CLOCK Registers
      5. 8.3.5  SYSREF Registers
      6. 8.3.6  JESD204C Registers
      7. 8.3.7  JESD204C_Advanced Registers
      8. 8.3.8  SerDes_Equalizer Registers
      9. 8.3.9  SerDes_Eye-Scan Registers
      10. 8.3.10 SerDes_Lane_Status Registers
      11. 8.3.11 SerDes_PLL Registers
      12. 8.3.12 DAC_and_Analog_Configuration Registers
      13. 8.3.13 Datapath Registers
      14. 8.3.14 NCO_and_Mixer Registers
      15. 8.3.15 Alarm Registers
      16. 8.3.16 Fuse_Control Registers
      17. 8.3.17 Fuse_Backed Registers
      18. 8.3.18 DDS_Vector_Mode Registers
      19. 8.3.19 Programmable_FIR Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Startup Procedure
      2. 9.1.2 Bandwidth Optimization for Square Wave Mode
    2. 9.2 Typical Application: Ku-Band Radar Transmitter
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Up and Down Sequence
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines and Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.18 DDS_Vector_Mode Registers

Table 8-313 lists the memory-mapped registers for the DDS_Vector_Mode registers. All register offset addresses not listed in Table 8-313 should be considered as reserved locations and the register contents should not be modified.

Table 8-313 DDS_VECTOR_MODE Registers
OffsetAcronymRegister NameSection
0x800DDS_BURST_0Section 8.3.18.1
0x802DDS_BURST_1Section 8.3.18.2
0x804DDS_BURST_2Section 8.3.18.3
0x806DDS_BURST_3Section 8.3.18.4
0x808DDS_IMODESection 8.3.18.5
0x809DDS_SYMSection 8.3.18.6
0x80ADDS_HOLDSection 8.3.18.7
0x80BDDS_IDLESection 8.3.18.8
0x80CDDS_INDEX0Section 8.3.18.9
0x80DDDS_INDEX1Section 8.3.18.10
0x80EDDS_INDEX2Section 8.3.18.11
0x80FDDS_INDEX3Section 8.3.18.12
0x810DDS_AMP2Section 8.3.18.13
0xB20DDS_VEC_nSection 8.3.18.14

Complex bit access types are encoded to fit into small table cells. Table 8-314 shows the codes that are used for access types in this section.

Table 8-314 DDS_Vector_Mode Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.3.18.1 DDS_BURST_0 Register (Offset = 0x800) [Reset = 0x0000]

DDS_BURST_0 is shown in Table 8-315.

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Table 8-315 DDS_BURST_0 Register Field Descriptions
BitFieldTypeResetDescription
15-0DDS_BURST[0]R/W0x0 Trigger burst control for DDS channel n. In DDS Vector Mode, DDS_BURST defines how many additional times a DDS channel is triggered when it receives a trigger event (see Trigger Burst). The additional triggers are queued and the DDS behaves like it received DDS_BURST+1 triggers. The legal range of DDS_BURST is 0 to 65535.
The user may change DDS_BURST while the DDS is enabled (SYS_EN=1), but must ensure that no trigger events occur during the SPI transaction, or for 50ns after the transaction is completed.

8.3.18.2 DDS_BURST_1 Register (Offset = 0x802) [Reset = 0x0000]

DDS_BURST_1 is shown in Table 8-316.

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Table 8-316 DDS_BURST_1 Register Field Descriptions
BitFieldTypeResetDescription
15-0DDS_BURST[1]R/W0x0 See description for DDS_BURST[0]

8.3.18.3 DDS_BURST_2 Register (Offset = 0x804) [Reset = 0x0000]

DDS_BURST_2 is shown in Table 8-317.

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Table 8-317 DDS_BURST_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0DDS_BURST[2]R/W0x0 See description for DDS_BURST[0]

8.3.18.4 DDS_BURST_3 Register (Offset = 0x806) [Reset = 0x0000]

DDS_BURST_3 is shown in Table 8-318.

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Table 8-318 DDS_BURST_3 Register Field Descriptions
BitFieldTypeResetDescription
15-0DDS_BURST[3]R/W0x0 See description for DDS_BURST[0]

8.3.18.5 DDS_IMODE Register (Offset = 0x808) [Reset = 0x00]

DDS_IMODE is shown in Table 8-319.

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Table 8-319 DDS_IMODE Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0
0DDS_IMODER/W0x0
  • 0x0 = Indexing-Mode Disabled. Up to 4 DDS channels can be enabled. DDS waits for triggers according to the VTRIG_MODE field of each vector.
  • 0x1 = Indexing-Mode Enabled. Only DDS channel 0 can be enabled, and all vector memory is assigned to it. The TRIG[4:1] inputs can be used jump to specific vectors on-demand. See Indexing-Mode Section for full details.

8.3.18.6 DDS_SYM Register (Offset = 0x809) [Reset = 0x00]

DDS_SYM is shown in Table 8-320.

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Table 8-320 DDS_SYM Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0DDS_SYMR/W0x0 DDS_SYM[n] enables symmetric mode for DDS channel n. See Vector Order and Symmetric Mode.

8.3.18.7 DDS_HOLD Register (Offset = 0x80A) [Reset = 0x00]

DDS_HOLD is shown in Table 8-321.

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Table 8-321 DDS_HOLD Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0DDS_HOLDR/W0x0 DDS_HOLD[n] enables hold mode for DDS channel n. See Hold Mode.

8.3.18.8 DDS_IDLE Register (Offset = 0x80B) [Reset = 0xXX]

DDS_IDLE is shown in Table 8-322.

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Table 8-322 DDS_IDLE Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDRX
3-0DDS_IDLERX DDS_IDLE[n] returns 1 if DDS channel n is currently idle (waiting for a trigger), otherwise it returns 0.

8.3.18.9 DDS_INDEX0 Register (Offset = 0x80C) [Reset = 0xXX]

DDS_INDEX0 is shown in Table 8-323.

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Table 8-323 DDS_INDEX0 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDRX
3-0DDS_INDEX0RX DDS_Index0 returns the index of the vector that DDS channel n is currently executing (or waiting for a trigger to execute).

8.3.18.10 DDS_INDEX1 Register (Offset = 0x80D) [Reset = 0xXX]

DDS_INDEX1 is shown in Table 8-324.

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Table 8-324 DDS_INDEX1 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDRX
3-0DDS_INDEX1RX See DDS_INDEX0

8.3.18.11 DDS_INDEX2 Register (Offset = 0x80E) [Reset = 0xXX]

DDS_INDEX2 is shown in Table 8-325.

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Table 8-325 DDS_INDEX2 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDRX
3-0DDS_INDEX2RX See DDS_INDEX0

8.3.18.12 DDS_INDEX3 Register (Offset = 0x80F) [Reset = 0xXX]

DDS_INDEX3 is shown in Table 8-326.

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Table 8-326 DDS_INDEX3 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDRX
3-0DDS_INDEX3RX See DDS_INDEX0

8.3.18.13 DDS_AMP2 Register (Offset = 0x810) [Reset = 0x00]

DDS_AMP2 is shown in Table 8-327.

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Table 8-327 DDS_AMP2 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0DDS_AMP2R/W0x0 DDS_AMP2[n] enables 2nd-order amplitude control for DDS channel n. This allows the vector mode to synthesize smooth and accurate amplitude curves.
Note: This register should only be changed when SYS_EN=0.

8.3.18.14 DDS_VEC_n Register (Offset = 0xB20) [Reset = 0xXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]

DDS_VEC_n is shown in Table 8-328.

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Table 8-328 DDS_VEC_n Register Field Descriptions
BitFieldTypeResetDescription
167-120FREQ_STARTR/WX Each vector is 21 bytes (168 bits) and the address for vector n starts at 0x0B10 + 21*n (21 is base 10 value). All 384 vectors occupy 8064 bytes.
Vectors are allocated to DDS channels depending on how many DDS channels are enabled. See section DDS Vector Mode for further details.
Note: Vectors can be updated via SPI while the DDS is enabled, but restrictions apply. See Writing Vectors While DDS is Enabled.
Initial value of frequency accumulator (48-bits).
Note: the lower 16-bits of FREQ_START can be repurposed for 2nd order amplitude control (AMP_STEP2, 16-bits, signed).
119-88FREQ_STEPR/WX Frequency step (32-bits)
87-72AMP_STARTR/WX Initial value of amplitude accumulator (16-bits, signed)
71-56AMP_STEPR/WX Amplitude step (16-bits, signed)
55-40PHASE_STARTR/WX Initial value of phase accumulator (16-bits)
39-8NUM_SAMP_M32 R/WX Vector length in samples minus 32 (32-bits). NUM_SAMP_M32 must be a multiple of 8 (# of samples minimum is 32). The lower 3 bits always return 0.
7-3STEP_EXPR/WX Defines exponent applied to frequency and amplitude step values. Legal range is 3 to 31 (or 3 to 15 if DDS_AMP2[n]=1).
2RESERVEDR0x0
1LAST_VECR/WX
  • 0x0 = Continue to next vector after playing this vector.
  • 0x1 = Return to start of Vector Block after playing this vector (or return to VINDEX in indexing-mode).
0VTRIG_MODER/WX
  • 0x0 = Auto-trigger (vector starts and ends automatically)
  • 0x1 = Manual trigger (DDS may stall until a trigger occurs)