SBASAO8 June   2025 DAC39RF20

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI Interface Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RF Mode
        3. 7.3.1.3 DES Modes
      2. 7.3.2  DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3  DEM and Dither
      4. 7.3.4  Offset Adjustment
      5. 7.3.5  Clocking Subsystem
        1. 7.3.5.1 Converter Phase Locked Loop (CPLL)
        2. 7.3.5.2 Clock and SYSREF Delay
        3. 7.3.5.3 SYSREF Capture and Monitoring
          1. 7.3.5.3.1 SYSREF Frequency Requirements
          2. 7.3.5.3.2 SYSREF Pulses for Full Alignment
          3. 7.3.5.3.3 Automatic SYSREF Calibration and Tracking
            1. 7.3.5.3.3.1 SYSREF Automatic Calibration Procedure
            2. 7.3.5.3.3.2 Multi-device Alignment
            3. 7.3.5.3.3.3 Calibration Failure
            4. 7.3.5.3.3.4 SYSREF Tracking
        4. 7.3.5.4 Trigger Clocking
      6. 7.3.6  Digital Signal Processing Blocks
        1. 7.3.6.1  Bypass Mode
        2. 7.3.6.2  DUC Mode
          1. 7.3.6.2.1 Digital Upconverter (DUC)
            1. 7.3.6.2.1.1 Interpolation Filters
            2. 7.3.6.2.1.2 Numerically Controlled Oscillator (NCO)
              1. 7.3.6.2.1.2.1 Phase-continuous NCO Update Mode
              2. 7.3.6.2.1.2.2 Phase-coherent NCO Update Mode
              3. 7.3.6.2.1.2.3 Phase-sync NCO Update Mode
              4. 7.3.6.2.1.2.4 NCO Synchronization
                1. 7.3.6.2.1.2.4.1 JESD204C LSB Synchronization
        3. 7.3.6.3  DDS SPI Mode
        4. 7.3.6.4  DDS Vector Mode
          1. 7.3.6.4.1 Second Order Amplitude Support
          2. 7.3.6.4.2 Vector Order and Symmetric Vector Mode
          3. 7.3.6.4.3 Initial Startup
          4. 7.3.6.4.4 Trigger Queuing
          5. 7.3.6.4.5 Trigger Burst
          6. 7.3.6.4.6 Hold Mode
          7. 7.3.6.4.7 Indexing Mode
          8. 7.3.6.4.8 Queued or Burst Triggers in Indexing-Mode
          9. 7.3.6.4.9 Writing Vectors While DDS is Enabled
        5. 7.3.6.5  DDS Streaming Mode
        6. 7.3.6.6  DSP Triggering
          1. 7.3.6.6.1 Trigger Latency
        7. 7.3.6.7  NCO Square Wave Mode
          1. 7.3.6.7.1 Square Wave Enable
        8. 7.3.6.8  DSP Mute Function
        9. 7.3.6.9  DSP Output Gain
        10. 7.3.6.10 Complex Output Support
        11. 7.3.6.11 Channel Bonder
        12. 7.3.6.12 Programmable FIR Filter
          1. 7.3.6.12.1 PFIR Coefficients
          2. 7.3.6.12.2 PFIR Reflection Cancellation Mode
          3. 7.3.6.12.3 PFIR Power Savings
          4. 7.3.6.12.4 PFIR Usage
        13. 7.3.6.13 DES Interpolator
          1. 7.3.6.13.1 DAC Mute Function
      7. 7.3.7  Serdes Physical Layer
        1. 7.3.7.1 Serdes PLL
          1. 7.3.7.1.1 Enabling the Serdes PLL
          2. 7.3.7.1.2 Reference Clock
          3. 7.3.7.1.3 PLL VCO Calibration
          4. 7.3.7.1.4 Serdes PLL Loop Bandwidth
        2. 7.3.7.2 Serdes Receiver
          1. 7.3.7.2.1 Serdes Data Rate Selection
          2. 7.3.7.2.2 Serdes Receiver Termination
          3. 7.3.7.2.3 Serdes Receiver Polarity
          4. 7.3.7.2.4 Serdes Clock Data Recovery
          5. 7.3.7.2.5 Serdes Equalizer
            1. 7.3.7.2.5.1 Adaptive Equalization
            2. 7.3.7.2.5.2 Fixed Equalization
            3. 7.3.7.2.5.3 Pre and Post Cursor Analysis
          6. 7.3.7.2.6 Serdes Receiver Eyescan
            1. 7.3.7.2.6.1 Eyescan Procedure
            2. 7.3.7.2.6.2 Building an Eye Diagram
        3. 7.3.7.3 Serdes PHY Status
      8. 7.3.8  JESD204C Interface
        1. 7.3.8.1 Deviation from JESD204C Standard
        2. 7.3.8.2 Link Layer
          1. 7.3.8.2.1 Serdes Crossbar
          2. 7.3.8.2.2 Bit Error Rate Tester
          3. 7.3.8.2.3 Scrambler and Descrambler
          4. 7.3.8.2.4 64b and 66b Decoding Link Layer
            1. 7.3.8.2.4.1 Sync Header Alignment
            2. 7.3.8.2.4.2 Extended Multiblock Alignment
            3. 7.3.8.2.4.3 Data Integrity
          5. 7.3.8.2.5 8B and 10B Encoding Link Layer
            1. 7.3.8.2.5.1 Code Group Synchronization (CGS)
            2. 7.3.8.2.5.2 Initial Lane Alignment Sequence (ILAS)
            3. 7.3.8.2.5.3 Multi-frames and the Local Multiframe Clock (LMFC)
            4. 7.3.8.2.5.4 Frame and Multiframe Monitoring
            5. 7.3.8.2.5.5 Link Restart
            6. 7.3.8.2.5.6 Link Error Reports
            7. 7.3.8.2.5.7 Watchdog Timer (JTIMER)
        3. 7.3.8.3 SYSREF Alignment Required in Subclass 1 Mode
        4. 7.3.8.4 Transport Layer
        5. 7.3.8.5 JESD204C Debug Capture (JCAP)
          1. 7.3.8.5.1 Physical Layer Debug Capture
          2. 7.3.8.5.2 Link Layer Debug Capture
          3. 7.3.8.5.3 Transport Layer Debug Capture
        6. 7.3.8.6 JESD204C Interface Modes
          1. 7.3.8.6.1 JESD204C Format Diagrams
            1. 7.3.8.6.1.1 16-bit Formats
            2. 7.3.8.6.1.2 12-bit Formats
            3. 7.3.8.6.1.3 8-bit Formats
          2. 7.3.8.6.2 DUC and DDS Modes
      9. 7.3.9  Data Path Latency
      10. 7.3.10 Multi-Device Synchronization and Deterministic Latency
        1. 7.3.10.1 Programming RBD
        2. 7.3.10.2 Multiframe Lengths less than 32 Octa-Bytes (256 Bytes)
        3. 7.3.10.3 Recommended Algorithm to Determine the RBD Value
        4. 7.3.10.4 Operation in Subclass 0 Systems
      11. 7.3.11 Link Reset
      12. 7.3.12 Alarm Generation
        1. 7.3.12.1 Over Range Detection
        2. 7.3.12.2 Over Range Masking
      13. 7.3.13 Mute Function
        1. 7.3.13.1 Alarm Data Path Muting
        2. 7.3.13.2 Transmit Enables
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
  9. 8 Programming
    1. 8.1 Using the Standard SPI Interface
      1. 8.1.1 SCS
      2. 8.1.2 SCLK
      3. 8.1.3 SDI
      4. 8.1.4 SDO
      5. 8.1.5 Serial Interface Protocol
      6. 8.1.6 Streaming Mode
    2. 8.2 Using the Fast Reconfiguration Interface
    3. 8.3 Register Maps
      1. 8.3.1  Standard_SPI-3.1 Registers
      2. 8.3.2  System Registers
      3. 8.3.3  Trigger Registers
      4. 8.3.4  CPLL_AND_CLOCK Registers
      5. 8.3.5  SYSREF Registers
      6. 8.3.6  JESD204C Registers
      7. 8.3.7  JESD204C_Advanced Registers
      8. 8.3.8  SerDes_Equalizer Registers
      9. 8.3.9  SerDes_Eye-Scan Registers
      10. 8.3.10 SerDes_Lane_Status Registers
      11. 8.3.11 SerDes_PLL Registers
      12. 8.3.12 DAC_and_Analog_Configuration Registers
      13. 8.3.13 Datapath Registers
      14. 8.3.14 NCO_and_Mixer Registers
      15. 8.3.15 Alarm Registers
      16. 8.3.16 Fuse_Control Registers
      17. 8.3.17 Fuse_Backed Registers
      18. 8.3.18 DDS_Vector_Mode Registers
      19. 8.3.19 Programmable_FIR Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Startup Procedure
      2. 9.1.2 Bandwidth Optimization for Square Wave Mode
    2. 9.2 Typical Application: Ku-Band Radar Transmitter
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Up and Down Sequence
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines and Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.3 Trigger Registers

Table 8-24 lists the memory-mapped registers for the Trigger registers. All register offset addresses not listed in Table 8-24 should be considered as reserved locations and the register contents should not be modified.

Table 8-24 TRIGGER Registers
OffsetAcronymRegister NameSection
0x40TRIGC_DIVSection 8.3.3.1
0x41TRIGC_OUT_ENSection 8.3.3.2
0x42TRIG_TYPESection 8.3.3.3
0x44TRIG_SPISection 8.3.3.4
0x45TRIG_SELSection 8.3.3.5
0x4FDSP_TRIG_DETSection 8.3.3.6
0x50FRS_RSection 8.3.3.7

Complex bit access types are encoded to fit into small table cells. Table 8-25 shows the codes that are used for access types in this section.

Table 8-25 Trigger Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value

8.3.3.1 TRIGC_DIV Register (Offset = 0x40) [Reset = 0x7F]

TRIGC_DIV is shown in Table 8-26.

Return to the Summary Table.

Table 8-26 TRIGC_DIV Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0
6-0TRIGC_DIVR/W0x7F FTRIGCLK = FDACCLK / 32 / (TRIGC_DIV+1)
Note: TRIGC_DIV should be programmed to keep the trigger clock frequency below 200 MHz.

8.3.3.2 TRIGC_OUT_EN Register (Offset = 0x41) [Reset = 0x00]

TRIGC_OUT_EN is shown in Table 8-27.

Return to the Summary Table.

Table 8-27 TRIGC_OUT_EN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0
0TRIGC_OUT_ENR/W0x0 The trigger clock is driven on the TRIGCLK output when SYS_EN = 1 .
Note: At least one TRIG_TYPEn must be 4 for TRIGCLK to operate.
Note: When FR_EN=1, TRIGC_OUT_EN is ignored and treated as if it is 0.

8.3.3.3 TRIG_TYPE Register (Offset = 0x42) [Reset = 0x0000]

TRIG_TYPE is shown in Table 8-28.

Return to the Summary Table.

Table 8-28 TRIG_TYPE Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0x0
14-12TRIG_TYPE3R/W0x0 TRIG_TYPEn chooses the type of trigger to use for DSPn. Each DSP channel can have a unique trigger type. See DSP Triggering for more information about which actions occur when a DSP is triggered. Some trigger types require the user to program TRIG_SELn to choose a trigger index for DSPn).
Note: The JESD204C LSB bits still pass to the DUC input (or DDS Streaming function) even when they are being used for a trigger. This has a negligible impact on the DUC input. When DDS Streaming is used, only STREAM_MODEn=1 is supported when TRIG_TYPEn=3. Note: This register should only be changed when SYS_EN=0.
  • 0x0 = SPI-immediate - A rising edge on TRIG_SPI[TRIG_SELn] will immediately trigger DSPn actions.
  • 0x1 = SYSREF One-Shot A rising edge on TRIG_SPI[TRIG_SELn] will trigger DSPn actions on the next SYSREF rising edge.
  • 0x2 = SYSREF Continuous - While TRIG_SPI[TRIG_SELn] is high, every SYSREF rising edge will trigger DSPn actions.
  • 0x3 = JESD204C LSB - While TRIG_SPI[TRIG_SELn] is high, the LSb of JESD204C samples from stream 0 will trigger DSPn actions. To initiate a trigger event, the LSb must be low for 4 consecutive samples and then go high for 4 consecutive samples. This setting is compatible with DDS stream modes only if DDS amplitude streaming is disabled for DDS0 (see DSP_MODE and AMP_STREAM).
  • 0x4 = A rising edge on TRIG[TRIG_SELn] will trigger DSPn actions. Not available when FR_EN is set to 1.
  • 0x5 = If FRS is set, then DSPn is triggered by the rising edge of frcs_n.
  • 0x6 = If FRS is set, then DSPn is triggered by the rising edge of trig_c that follows the rising edge of frcs_n (one-shot).
  • 0x7 = RESERVED
11RESERVEDR0x0
10-8TRIG_TYPE2R/W0x0 See TRIG_TYPE3 description
7RESERVEDR0x0
6-4TRIG_TYPE1R/W0x0 See TRIG_TYPE3 description
3RESERVEDR0x0
2-0TRIG_TYPE0R/W0x0 See TRIG_TYPE3 description

8.3.3.4 TRIG_SPI Register (Offset = 0x44) [Reset = 0x00]

TRIG_SPI is shown in Table 8-29.

Return to the Summary Table.

Table 8-29 TRIG_SPI Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0TRIG_SPIR/W0x0 These bits are used to trigger or enable trigger sources for DSP channels. The TRIG_TYPEn registers determines how TRIG_SPI is used. TRIG_SPI[TRIG_SELn] affects DSPn. See DSP Triggering.
Note: These register bits are edge or level sensitive depending on the setting for TRIG_TYPE.

8.3.3.5 TRIG_SEL Register (Offset = 0x45) [Reset = 0x00]

TRIG_SEL is shown in Table 8-30.

Return to the Summary Table.

Table 8-30 TRIG_SEL Register Field Descriptions
BitFieldTypeResetDescription
7-6TRIG_SEL3R/W0x0 Determine which TRIG_SPI bit or which external trigger (TRIG) is bound to DSP channel 3
5-4TRIG_SEL2R/W0x0 Determine which TRIG_SPI bit or which external trigger (TRIG) is bound to DSP channel 2
3-2TRIG_SEL1R/W0x0 Determine which TRIG_SPI bit or which external trigger (TRIG) is bound to DSP channel 1
1-0TRIG_SEL0R/W0x0 Determine which TRIG_SPI bit or which external trigger (TRIG) is bound to DSP channel 0

8.3.3.6 DSP_TRIG_DET Register (Offset = 0x4F) [Reset = 0x00]

DSP_TRIG_DET is shown in Table 8-31.

Return to the Summary Table.

Table 8-31 DSP_TRIG_DET Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0 Reserved
0DSP_TRIG_DETR/W1C0x0 This bit is set any time one or more DSPs receives a trigger event. Write 1 to clear.

8.3.3.7 FRS_R Register (Offset = 0x50) [Reset = 0xXX]

FRS_R is shown in Table 8-32.

Return to the Summary Table.

Table 8-32 FRS_R Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDRX Reserved
0FRS_RRX This provides readback for the value of FRS in the last FRI transaction