SBASAO8 June   2025 DAC39RF20

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI Interface Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RF Mode
        3. 7.3.1.3 DES Modes
      2. 7.3.2  DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3  DEM and Dither
      4. 7.3.4  Offset Adjustment
      5. 7.3.5  Clocking Subsystem
        1. 7.3.5.1 Converter Phase Locked Loop (CPLL)
        2. 7.3.5.2 Clock and SYSREF Delay
        3. 7.3.5.3 SYSREF Capture and Monitoring
          1. 7.3.5.3.1 SYSREF Frequency Requirements
          2. 7.3.5.3.2 SYSREF Pulses for Full Alignment
          3. 7.3.5.3.3 Automatic SYSREF Calibration and Tracking
            1. 7.3.5.3.3.1 SYSREF Automatic Calibration Procedure
            2. 7.3.5.3.3.2 Multi-device Alignment
            3. 7.3.5.3.3.3 Calibration Failure
            4. 7.3.5.3.3.4 SYSREF Tracking
        4. 7.3.5.4 Trigger Clocking
      6. 7.3.6  Digital Signal Processing Blocks
        1. 7.3.6.1  Bypass Mode
        2. 7.3.6.2  DUC Mode
          1. 7.3.6.2.1 Digital Upconverter (DUC)
            1. 7.3.6.2.1.1 Interpolation Filters
            2. 7.3.6.2.1.2 Numerically Controlled Oscillator (NCO)
              1. 7.3.6.2.1.2.1 Phase-continuous NCO Update Mode
              2. 7.3.6.2.1.2.2 Phase-coherent NCO Update Mode
              3. 7.3.6.2.1.2.3 Phase-sync NCO Update Mode
              4. 7.3.6.2.1.2.4 NCO Synchronization
                1. 7.3.6.2.1.2.4.1 JESD204C LSB Synchronization
        3. 7.3.6.3  DDS SPI Mode
        4. 7.3.6.4  DDS Vector Mode
          1. 7.3.6.4.1 Second Order Amplitude Support
          2. 7.3.6.4.2 Vector Order and Symmetric Vector Mode
          3. 7.3.6.4.3 Initial Startup
          4. 7.3.6.4.4 Trigger Queuing
          5. 7.3.6.4.5 Trigger Burst
          6. 7.3.6.4.6 Hold Mode
          7. 7.3.6.4.7 Indexing Mode
          8. 7.3.6.4.8 Queued or Burst Triggers in Indexing-Mode
          9. 7.3.6.4.9 Writing Vectors While DDS is Enabled
        5. 7.3.6.5  DDS Streaming Mode
        6. 7.3.6.6  DSP Triggering
          1. 7.3.6.6.1 Trigger Latency
        7. 7.3.6.7  NCO Square Wave Mode
          1. 7.3.6.7.1 Square Wave Enable
        8. 7.3.6.8  DSP Mute Function
        9. 7.3.6.9  DSP Output Gain
        10. 7.3.6.10 Complex Output Support
        11. 7.3.6.11 Channel Bonder
        12. 7.3.6.12 Programmable FIR Filter
          1. 7.3.6.12.1 PFIR Coefficients
          2. 7.3.6.12.2 PFIR Reflection Cancellation Mode
          3. 7.3.6.12.3 PFIR Power Savings
          4. 7.3.6.12.4 PFIR Usage
        13. 7.3.6.13 DES Interpolator
          1. 7.3.6.13.1 DAC Mute Function
      7. 7.3.7  Serdes Physical Layer
        1. 7.3.7.1 Serdes PLL
          1. 7.3.7.1.1 Enabling the Serdes PLL
          2. 7.3.7.1.2 Reference Clock
          3. 7.3.7.1.3 PLL VCO Calibration
          4. 7.3.7.1.4 Serdes PLL Loop Bandwidth
        2. 7.3.7.2 Serdes Receiver
          1. 7.3.7.2.1 Serdes Data Rate Selection
          2. 7.3.7.2.2 Serdes Receiver Termination
          3. 7.3.7.2.3 Serdes Receiver Polarity
          4. 7.3.7.2.4 Serdes Clock Data Recovery
          5. 7.3.7.2.5 Serdes Equalizer
            1. 7.3.7.2.5.1 Adaptive Equalization
            2. 7.3.7.2.5.2 Fixed Equalization
            3. 7.3.7.2.5.3 Pre and Post Cursor Analysis
          6. 7.3.7.2.6 Serdes Receiver Eyescan
            1. 7.3.7.2.6.1 Eyescan Procedure
            2. 7.3.7.2.6.2 Building an Eye Diagram
        3. 7.3.7.3 Serdes PHY Status
      8. 7.3.8  JESD204C Interface
        1. 7.3.8.1 Deviation from JESD204C Standard
        2. 7.3.8.2 Link Layer
          1. 7.3.8.2.1 Serdes Crossbar
          2. 7.3.8.2.2 Bit Error Rate Tester
          3. 7.3.8.2.3 Scrambler and Descrambler
          4. 7.3.8.2.4 64b and 66b Decoding Link Layer
            1. 7.3.8.2.4.1 Sync Header Alignment
            2. 7.3.8.2.4.2 Extended Multiblock Alignment
            3. 7.3.8.2.4.3 Data Integrity
          5. 7.3.8.2.5 8B and 10B Encoding Link Layer
            1. 7.3.8.2.5.1 Code Group Synchronization (CGS)
            2. 7.3.8.2.5.2 Initial Lane Alignment Sequence (ILAS)
            3. 7.3.8.2.5.3 Multi-frames and the Local Multiframe Clock (LMFC)
            4. 7.3.8.2.5.4 Frame and Multiframe Monitoring
            5. 7.3.8.2.5.5 Link Restart
            6. 7.3.8.2.5.6 Link Error Reports
            7. 7.3.8.2.5.7 Watchdog Timer (JTIMER)
        3. 7.3.8.3 SYSREF Alignment Required in Subclass 1 Mode
        4. 7.3.8.4 Transport Layer
        5. 7.3.8.5 JESD204C Debug Capture (JCAP)
          1. 7.3.8.5.1 Physical Layer Debug Capture
          2. 7.3.8.5.2 Link Layer Debug Capture
          3. 7.3.8.5.3 Transport Layer Debug Capture
        6. 7.3.8.6 JESD204C Interface Modes
          1. 7.3.8.6.1 JESD204C Format Diagrams
            1. 7.3.8.6.1.1 16-bit Formats
            2. 7.3.8.6.1.2 12-bit Formats
            3. 7.3.8.6.1.3 8-bit Formats
          2. 7.3.8.6.2 DUC and DDS Modes
      9. 7.3.9  Data Path Latency
      10. 7.3.10 Multi-Device Synchronization and Deterministic Latency
        1. 7.3.10.1 Programming RBD
        2. 7.3.10.2 Multiframe Lengths less than 32 Octa-Bytes (256 Bytes)
        3. 7.3.10.3 Recommended Algorithm to Determine the RBD Value
        4. 7.3.10.4 Operation in Subclass 0 Systems
      11. 7.3.11 Link Reset
      12. 7.3.12 Alarm Generation
        1. 7.3.12.1 Over Range Detection
        2. 7.3.12.2 Over Range Masking
      13. 7.3.13 Mute Function
        1. 7.3.13.1 Alarm Data Path Muting
        2. 7.3.13.2 Transmit Enables
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
  9. 8 Programming
    1. 8.1 Using the Standard SPI Interface
      1. 8.1.1 SCS
      2. 8.1.2 SCLK
      3. 8.1.3 SDI
      4. 8.1.4 SDO
      5. 8.1.5 Serial Interface Protocol
      6. 8.1.6 Streaming Mode
    2. 8.2 Using the Fast Reconfiguration Interface
    3. 8.3 Register Maps
      1. 8.3.1  Standard_SPI-3.1 Registers
      2. 8.3.2  System Registers
      3. 8.3.3  Trigger Registers
      4. 8.3.4  CPLL_AND_CLOCK Registers
      5. 8.3.5  SYSREF Registers
      6. 8.3.6  JESD204C Registers
      7. 8.3.7  JESD204C_Advanced Registers
      8. 8.3.8  SerDes_Equalizer Registers
      9. 8.3.9  SerDes_Eye-Scan Registers
      10. 8.3.10 SerDes_Lane_Status Registers
      11. 8.3.11 SerDes_PLL Registers
      12. 8.3.12 DAC_and_Analog_Configuration Registers
      13. 8.3.13 Datapath Registers
      14. 8.3.14 NCO_and_Mixer Registers
      15. 8.3.15 Alarm Registers
      16. 8.3.16 Fuse_Control Registers
      17. 8.3.17 Fuse_Backed Registers
      18. 8.3.18 DDS_Vector_Mode Registers
      19. 8.3.19 Programmable_FIR Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Startup Procedure
      2. 9.1.2 Bandwidth Optimization for Square Wave Mode
    2. 9.2 Typical Application: Ku-Band Radar Transmitter
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Up and Down Sequence
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines and Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.12 DAC_and_Analog_Configuration Registers

Table 8-223 lists the memory-mapped registers for the DAC_and_Analog_Configuration registers. All register offset addresses not listed in Table 8-223 should be considered as reserved locations and the register contents should not be modified.

Table 8-223 DAC_AND_ANALOG_CONFIGURATION Registers
OffsetAcronymRegister NameSection
0x280CURRENT_2XSection 8.3.12.1
0x2A0DACA_CURRENTSection 8.3.12.2
0x2A1DACB_CURRENTSection 8.3.12.3
0x2AFCS_AMP_FILTERSection 8.3.12.4
0x2B0EXTREF_ENSection 8.3.12.5
0x2C0NOISEREDUCE_EN0Section 8.3.12.6
0x2C1NOISEREDUCE_EN1Section 8.3.12.7
0x2CFDAC_OFS_CHG_BLKSection 8.3.12.8

Complex bit access types are encoded to fit into small table cells. Table 8-224 shows the codes that are used for access types in this section.

Table 8-224 DAC_and_Analog_Configuration Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.3.12.1 CURRENT_2X Register (Offset = 0x280) [Reset = 0x00]

CURRENT_2X is shown in Table 8-225.

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Table 8-225 CURRENT_2X Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0 Reserved
0CURRENT_2X_ENR/W0x0
  • 0x0 = Enables 2x current mode for both DACs.
  • 0x1 = Disables 2x current mode for both DACs.

8.3.12.2 DACA_CURRENT Register (Offset = 0x2A0) [Reset = 0x0F]

DACA_CURRENT is shown in Table 8-226.

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Table 8-226 DACA_CURRENT Register Field Descriptions
BitFieldTypeResetDescription
7-4COARSE_CUR_A_SLEEPR/W0x0 Coarse current control for DACA in sleep mode
3-0COARSE_CUR_AR/W0xF Coarse current control for DACA in active mode

8.3.12.3 DACB_CURRENT Register (Offset = 0x2A1) [Reset = 0x0F]

DACB_CURRENT is shown in Table 8-227.

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Table 8-227 DACB_CURRENT Register Field Descriptions
BitFieldTypeResetDescription
7-4COARSE_CUR_B_SLEEPR/W0x0 Coarse current control for DACB in sleep mode
3-0COARSE_CUR_BR/W0xF Coarse current control for DACB in active mode

8.3.12.4 CS_AMP_FILTER Register (Offset = 0x2AF) [Reset = 0x00]

CS_AMP_FILTER is shown in Table 8-228.

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Table 8-228 CS_AMP_FILTER Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-2CS_AMP_FILTER1R/W0x0 Adjusts the cutoff frequency of a low-pass filter in the current source biasing path for DACB. The higher the setting, the lower the bandwidth in the current source path which supresses the 1/f noise, but startup time is longer.
  • 0x0 = cutoff at 20KHz (default)
  • 0x1 = cutoff at 4KHz
  • 0x2 = cutoff at 800Hz
  • 0x3 = cutoff at 1Hz
1-0CS_AMP_FILTER0R/W0x0 Adjusts the cutoff frequency of a low-pass filter in the current source biasing path for DACA. see CS_AMP_FILTER1.

8.3.12.5 EXTREF_EN Register (Offset = 0x2B0) [Reset = 0x00]

EXTREF_EN is shown in Table 8-229.

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Table 8-229 EXTREF_EN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0
0EXTREF_ENR/W0x0 Enables external reference

8.3.12.6 NOISEREDUCE_EN0 Register (Offset = 0x2C0) [Reset = 0xFF]

NOISEREDUCE_EN0 is shown in Table 8-230.

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Table 8-230 NOISEREDUCE_EN0 Register Field Descriptions
BitFieldTypeResetDescription
7-6NOISEREDUCE_IO18_ENR/W0x3 Reduces noise on the 1.8V VDDIO supply.
5NOISEREDUCE_CLKDRV_DACB_ENR/W0x1 Reduces noise on the DACB Clock Driver supplies (AVDDCLK).
4NOISEREDUCE_CLKDRV_DACA_ENR/W0x1 Reduces noise on the DACA Clock Driver supplies (AVDDCLK).
3-2NOISEREDUCE_MUX_DACB_ENR/W0x3 Reduces noise on the DACB MUX supplies. Set both bits to the same value.
1-0NOISEREDUCE_MUX_DACA_ENR/W0x3 Reduces noise on the DACA MUX supplies. Set both bits to the same value.

8.3.12.7 NOISEREDUCE_EN1 Register (Offset = 0x2C1) [Reset = 0x0F]

NOISEREDUCE_EN1 is shown in Table 8-231.

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Table 8-231 NOISEREDUCE_EN1 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-2NOISEREDUCE_SWDRV_DACB_ENR/W0x3 Reduces noise on the DACB Switch Driver supplies. Set both bits to the same value.
1-0NOISEREDUCE_SWDRV_DACA_ENR/W0x3 Reduces noise on the DACA Switch Driver supplies. Set both bits to the same value.

8.3.12.8 DAC_OFS_CHG_BLK Register (Offset = 0x2CF) [Reset = 0x00]

DAC_OFS_CHG_BLK is shown in Table 8-232.

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Table 8-232 DAC_OFS_CHG_BLK Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0
0DAC_OFS_CHG_BLKR/W0x0 When set, changes to DAC_OFS[n] are not propagated to the high-speed clocks and both DACs continue to use their current value. When this is changed from 1 to 0 the new DAC_OFS[n] values will be applied to both DACs. There can be a small time offset when the new values are applied to each DAC (10's of CLK cycles).