SPRACU5E June   2021  – October 2025 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 User's Guide Usage Guidelines
      1. 1.1.1 Custom Board Schematics Design Guidelines - References Used in the User's Guide
      2. 1.1.2 Processor Family (Families) Specific User's Guide
      3. 1.1.3 Schematic Design Guidelines
      4. 1.1.4 Schematic Review Checklist
        1. 1.1.4.1 Common Checklist for Use With All Schematic Design Guidelines and Schematics Review Sections
          1. 1.1.4.1.1 Custom Board Schematic Design Implementation Checklist Sub-Sections Description
      5. 1.1.5 FAQ Reference for User's Guide Usage During Schematic Self-review
    2. 1.2 Processor Family List of Processors
      1. 1.2.1 AM64x [ALV] Processor Family
      2. 1.2.2 AM243x [ALV] Processor Family
    3. 1.3 Updates to Schematics Design Guidelines and Schematics Review Checklist
  5. 2 Related Collateral
    1. 2.1 Links to Commonly Referenced Collaterals During Custom Board Schematic Design
    2. 2.2 Hardware Design Considerations for Custom Board Design User's Guide
  6. 3 Processor-Specific Information
    1. 3.1 Selection of Processor OPN (Orderable Part Number)
    2. 3.2 Processor-specific Data Sheet Use Case and Version Referenced for User's Guide Edits
    3. 3.3 Peripheral Instance Naming Convention - Data Sheet and TRM
    4. 3.4 Processor Peripherals and IOs Connection When Not Used (Unused)
    5. 3.5 Ordering and Quality Information for AM64x and AM243x Processor Families
    6. 3.6 Checklist for Selection of Required Processor GPN (Generic Part Number) and OPN (Ordering Part Number)
  7. 4 Processor Power Architecture
    1. 4.1 Generating Processor-Specific and Peripherals (Attached Device) Supply Rails
      1. 4.1.1 Power Management IC (PMIC) Based Power Architecture
        1. 4.1.1.1 PMIC Based Power Architecture Checklist for TPS65219 or TPS65220
        2. 4.1.1.2 Additional References
      2. 4.1.2 Discrete Power Devices (DC/DC, LDO) Based Power Architecture
        1. 4.1.2.1 Discrete DC/DCs
        2. 4.1.2.2 Discrete LDOs
        3. 4.1.2.3 Discrete Power Devices (DC/DC, LDO) Based Power Architecture Checklist
    2. 4.2 Processor Power Rails Supply Control, Sequencing and Supply Overload Protection
      1. 4.2.1 Load Switch (Processor Supply Rail Power Switching)
        1. 4.2.1.1 Load Switch (Processor Supply Rail Power Switching) Checklist
      2. 4.2.2 eFuse IC (Power Switching and Protection)
  8. 5 General Recommendations
    1. 5.1 Processor Performance Evaluation Module (EVM) or Starter Kit (SK)
      1. 5.1.1 Evaluation Module (Starter Kit) Checklist
    2. 5.2 Processor-Specific EVM or SK Versus Data Sheet
      1. 5.2.1 Notes About Component Selection
        1. 5.2.1.1 Series Resistor
        2. 5.2.1.2 Parallel Pull Resistor
        3. 5.2.1.3 Drive Strength Configuration
        4. 5.2.1.4 Processor-specific Data Sheet Recommendations
        5. 5.2.1.5 Processor IOs Protection - Provision for External ESD Protection Devices
        6. 5.2.1.6 Peripheral Clock Outputs Series Resistor
        7. 5.2.1.7 Peripheral Clock Outputs Pulldown Resistor
        8. 5.2.1.8 Component Selection Checklist
      2. 5.2.2 Additional Information Regarding EVM or SK Design (Schematic, Board) and Reuse
        1. 5.2.2.1 Updated EVM or SK Schematic With Design, Review and CAD Notes Added
        2. 5.2.2.2 EVM or SK Design Files Reuse for Custom Board Design
          1. 5.2.2.2.1 EVM or SK Design Files Reuse for Custom board Design - Checklist
      3. 5.2.3 EVM or SK Schematic Pages Sequencing (Based on Functions, Reuse) and EVM or SK Board Layout
    3. 5.3 Processor-Specific SDK
    4. 5.4 General Design Recommendations (to Know) Before Starting the Custom Board Design
      1. 5.4.1  Processor Documentation
      2. 5.4.2  Processor Pin Attributes (Pinout) Verification
      3. 5.4.3  Device Comparison, IOSET and Voltage Conflict
      4. 5.4.4  RSVD Reserved Pins (Signals)
      5. 5.4.5  Note on PADCONFIG Registers
      6. 5.4.6  Processor IO (Signal) Isolation for Fail-Safe Operation
      7. 5.4.7  Pin Connectivity Requirements and Reference to Processor-Specific EVM or SK
      8. 5.4.8  Custom Board High-Speed Interface Design Guidelines
      9. 5.4.9  Recommendation for LVCMOS (GPIO) Output Current Source or Current Sink
      10. 5.4.10 Connection of Slow Ramp Signal (Input) or Capacitor Load (Output) to Processor IOs
      11. 5.4.11 Processor and Processor Peripherals Design Related Queries During Custom Board Design
      12. 5.4.12 General Design Recommendations (to Know) Before Starting the Custom Board Design Checklist
      13. 5.4.13 Attached Devices Recommendations
  9. 6 Processor-Specific Recommendations for Power, Clock, Reset, Boot and Debug
    1. 6.1 Common (Processor Start-Up) Connections
      1. 6.1.1 Power Supply
        1. 6.1.1.1 Core and Peripherals Supplies
          1. 6.1.1.1.1 Power Supply Ramp (Slew Rate) Requirement and Dynamic Voltage Scaling
          2. 6.1.1.1.2 Additional Information
          3. 6.1.1.1.3 Processor Core and Peripheral Core Power Supply Checklist
          4. 6.1.1.1.4 Peripheral Analog Power Supply Checklist
        2. 6.1.1.2 IO Supply for IO Groups
          1. 6.1.1.2.1 IO Supply for IO Groups Checklist
        3. 6.1.1.3 Supply for VPP (eFuse ROM Programming)
          1. 6.1.1.3.1 Supply for VPP Checklist
        4. 6.1.1.4 Additional Information
      2. 6.1.2 Capacitors for Supply Rails
        1. 6.1.2.1 Additional Information
        2. 6.1.2.2 Capacitors for Supply Rails Checklist
      3. 6.1.3 Processor Clocks (Inputs / Outputs)
        1. 6.1.3.1 Clock Inputs
          1. 6.1.3.1.1 MCU_OSC0 (High Frequency) Clock (Internal Oscillator) or LVCMOS Digital Clock (External Oscillator)
          2. 6.1.3.1.2 EXT_REFCLK1 (External Clock Input to MAIN Domain)
          3. 6.1.3.1.3 Clock Input Checklist - MCU_OSC0
        2. 6.1.3.2 Clock Output
          1. 6.1.3.2.1 Clock Output Checklist
      4. 6.1.4 Processor Reset
        1. 6.1.4.1 External Reset Inputs
        2. 6.1.4.2 Reset Status Outputs
        3. 6.1.4.3 Additional Information
        4. 6.1.4.4 Processor Reset Inputs Checklist
        5. 6.1.4.5 Processor Reset Status Outputs Checklist
      5. 6.1.5 Configuration of Boot Modes (for Processor)
        1. 6.1.5.1 Processor Boot Mode Inputs Isolation Buffers Use Case and Optimization
        2. 6.1.5.2 Boot Mode Configuration
          1. 6.1.5.2.1 Notes for USB Boot Mode
        3. 6.1.5.3 Boot Mode Implementation Approaches
        4. 6.1.5.4 Additional Information
        5. 6.1.5.5 Configuration of Boot Modes (for Processor) Checklist
    2. 6.2 Custom Board Debug Using JTAG and EMU
      1. 6.2.1 JTAG Interface and EMU Signals When Used
      2. 6.2.2 JTAG Interface and EMU Signals When Not Used
      3. 6.2.3 Additional Information
      4. 6.2.4 Custom Board Debug Using JTAG and EMU Checklist
  10. 7 Processor Peripherals Power, Interface and Connections
    1. 7.1 Supported Processor Cores and MCU Cores
    2. 7.2 Supply Connections for IO Supply for IO Groups
      1. 7.2.1 Supply Connections for IO Supply for IO Groups Checklist
    3. 7.3 Memory Interface (DDRSS (DDR4/LPDDR4), MMCSD (eMMC/SD Card/SDIO), OSPI/QSPI and GPMC)
      1. 7.3.1 DDR Subsystem (DDRSS)
        1. 7.3.1.1 DDR4 SDRAM (Double Data Rate 4 Synchronous Dynamic Random-Access Memory)
          1. 7.3.1.1.1 Memory Interface Configuration
          2. 7.3.1.1.2 Routing Topology and Connection of Memory Terminations
          3. 7.3.1.1.3 Resistors for DDRSS Control and Calibration
          4. 7.3.1.1.4 Capacitors for the Power Supply Rails
          5. 7.3.1.1.5 Data Bit or Byte Swapping
          6. 7.3.1.1.6 DDR4 Implementation Checklist
          7. 7.3.1.1.7 DDR4 VTT Termination Implementation Schematic Reference
        2. 7.3.1.2 LPDDR4 SDRAM (Low-Power Double Data Rate 4 Synchronous Dynamic Random-Access Memory)
          1. 7.3.1.2.1 Memory Interface Configuration
          2. 7.3.1.2.2 Routing Topology and Connection of Memory Terminations
          3. 7.3.1.2.3 Resistors for DDRSS Control and Calibration
          4. 7.3.1.2.4 Capacitors for the Power Supply Rails
          5. 7.3.1.2.5 Data Bit or Byte Swapping
          6. 7.3.1.2.6 LPDDR4 Implementation Checklist
      2. 7.3.2 Multi-Media Card and Secure Digital (MMCSD)
        1. 7.3.2.1 MMC0 - eMMC (Embedded Multimedia Card) Interface
          1. 7.3.2.1.1 MMC0 Interface Used
            1. 7.3.2.1.1.1 IO Power Supply
            2. 7.3.2.1.1.2 eMMC Interface Signals Connection
            3. 7.3.2.1.1.3 eMMC (Attached Device) Reset
            4. 7.3.2.1.1.4 Capacitors for the Power Supply Rails
          2. 7.3.2.1.2 MMC0 Interface Not Used
          3. 7.3.2.1.3 MMC0 (eMMC) Checklist
          4. 7.3.2.1.4 Additional Information on eMMC PHY
          5. 7.3.2.1.5 MMC0 – SD (Secure Digital) Card Interface
        2. 7.3.2.2 MMC1 – SD (Secure Digital) Card Interface
          1. 7.3.2.2.1 IO Power Supply
          2. 7.3.2.2.2 Signals Connection
          3. 7.3.2.2.3 SD Card Power Supply Switch EN Reset Logic
          4. 7.3.2.2.4 External ESD Protection for the SD Card Interface Signals
          5. 7.3.2.2.5 Capacitors for the IO Supply for IO Groups Supply Rails
          6. 7.3.2.2.6 SD Card Interface (MMC1) Checklist
        3. 7.3.2.3 Additional Information
      3. 7.3.3 Octal Serial Peripheral Interface (OSPI) or Quad Serial Peripheral Interface (QSPI)
        1. 7.3.3.1 IO Power Supply
        2. 7.3.3.2 Signals Connection
        3. 7.3.3.3 OSPI/QSPI Device Reset
        4. 7.3.3.4 Loopback Clock
        5. 7.3.3.5 Interface to Multiple (Attached) Devices
        6. 7.3.3.6 Capacitors for the Power Supply Rails
        7. 7.3.3.7 OSPI0 or QSPI0 Peripheral Interface Implementation Checklist
      4. 7.3.4 General-Purpose Memory Controller (GPMC)
        1. 7.3.4.1 IO Power Supply
        2. 7.3.4.2 GPMC Interface
        3. 7.3.4.3 Signals Connection
          1. 7.3.4.3.1 GPMC NAND
        4. 7.3.4.4 Memory (Attached Device) Reset
        5. 7.3.4.5 Capacitors for the Power Supply Rails
        6. 7.3.4.6 GPMC Interface Checklist
    4. 7.4 External Communication Interface (Ethernet (CPSW3G0 and PRU_ICSSG), USB2.0, USB3.0 (SERDES0), PCIe (SERDES0), UART and MCAN)
      1. 7.4.1 Ethernet Interface
        1. 7.4.1.1  IO Power Supply
        2. 7.4.1.2  Media Independent Interface (MAC side)
          1. 7.4.1.2.1 Common Platform Ethernet Switch 3-Port Gigabit (CPSW3G0)
          2. 7.4.1.2.2 Programmable Real-Time Unit and Industrial Communication Subsystem - Gigabit (PRU_ICSSG)
          3. 7.4.1.2.3 Additional Information
        3. 7.4.1.3  Usage of SysConfig-PinMux Tool
        4. 7.4.1.4  MAC (Data, Control and Clock) Interface Signals Connection
        5. 7.4.1.5  EPHY Reset
        6. 7.4.1.6  Ethernet PHY (and MAC) Operation and Media Independent Interface (MII) Clock
          1. 7.4.1.6.1 Crystal Used as Clock Source for Processor and EPHYs
          2. 7.4.1.6.2 External Oscillator Used as Clock Source
          3. 7.4.1.6.3 Processor Clock Output (CLKOUT0)
        7. 7.4.1.7  Ethernet PHY Pin Strapping
        8. 7.4.1.8  External Interrupt (EXTINTn)
          1. 7.4.1.8.1 External Interrupt (EXTINTn) Checklist
        9. 7.4.1.9  MAC (Media Access Controller) to MAC Interface
        10. 7.4.1.10 MDIO (Management Data Input/Output) Interface
          1. 7.4.1.10.1 MDIO Interface Mode
        11. 7.4.1.11 Ethernet MDI (Medium Dependent Interface) Including Magnetics
        12. 7.4.1.12 Capacitors for the Power Supply Rails
        13. 7.4.1.13 Ethernet Interface Checklist
      2. 7.4.2 Universal Serial Bus (USB2.0)
        1. 7.4.2.1 USB0 Interface When Used
          1. 7.4.2.1.1 USB Interface Configured as Host
          2. 7.4.2.1.2 USB Interface Configured as Device
          3. 7.4.2.1.3 USB Interface Configured as Dual-Role-Device
          4. 7.4.2.1.4 USB Type-C
        2. 7.4.2.2 USB0 Interface When Not Used
        3. 7.4.2.3 Additional Information
        4. 7.4.2.4 USB Interface Checklist
      3. 7.4.3 Serializer and Deserializer (SERDES0)
        1. 7.4.3.1 SERDES0 Checklist
        2. 7.4.3.2 SERDES0 When Used
          1. 7.4.3.2.1 USB3SS0 - USB3.0 Super Speed Interface Configuration
            1. 7.4.3.2.1.1 Signal Interface
              1. 7.4.3.2.1.1.1 USB3.0 Super Speed Interface
                1. 7.4.3.2.1.1.1.1 USB3.0 Super Speed Interface Operating Mode Configuration
            2. 7.4.3.2.1.2 Unused SERDES0 Clock Connection
            3. 7.4.3.2.1.3 Additional Information
            4. 7.4.3.2.1.4 USB3SS0 - USB3.0 Super Speed Interface Checklist
          2. 7.4.3.2.2 Peripheral Component Interconnect Express (PCIe) Interface Configuration
            1. 7.4.3.2.2.1 Clock Configuration for PCIe Operating Modes
            2. 7.4.3.2.2.2 Signal Interface Termination
            3. 7.4.3.2.2.3 PCIe Clock (REFCLK) Source
            4. 7.4.3.2.2.4 Hardware Reset (Cold or Fundamental Reset)
            5. 7.4.3.2.2.5 PCIe Clock Request (PCIE0_CLKREQn) Signal
            6. 7.4.3.2.2.6 Connecting PCIe Interface Signals
            7. 7.4.3.2.2.7 PCIe Interface Checklist
        3. 7.4.3.3 SERDES0 Not Used
      4. 7.4.4 Universal Asynchronous Receiver/Transmitter (UART)
        1. 7.4.4.1 UART Interface When Not Used
        2. 7.4.4.2 Universal Asynchronous Receiver/Transmitter (UART) Checklist
      5. 7.4.5 Modular Controller Area Network (MCAN) with Full CAN-FD Support
        1. 7.4.5.1 Modular Controller Area Network Checklist
    5. 7.5 On-Board Synchronous Communication Interface (MCSPI, FSI and I2C)
      1. 7.5.1 Multichannel Serial Peripheral Interface (MCSPI)
        1. 7.5.1.1 Connection of MCSPI Interface Signals
        2. 7.5.1.2 MCSPI Interface Checklist
      2. 7.5.2 FSI (Fast Serial Interface)
        1. 7.5.2.1 FSI0 Checklist
      3. 7.5.3 Inter-Integrated Circuit (I2C)
        1. 7.5.3.1 I2C Interface Signals Connection
        2. 7.5.3.2 I2C (Open-drain Output Type IO Buffer) Interface Checklist
        3. 7.5.3.3 I2C (Emulated Open-drain Output Type IO) Interface Checklist
    6. 7.6 Analog to Digital Converter (ADC)
      1. 7.6.1 ADC0 When Used
      2. 7.6.2 ADC0 When Not Used
      3. 7.6.3 ADC0 Configured as Inputs ADC0_DIG_TEST[0-7]
      4. 7.6.4 ADC0 Checklist
    7. 7.7 GPIO and Hardware Diagnostics
      1. 7.7.1 General Purpose Input/Output (GPIO)
        1. 7.7.1.1 GPIO Connection and Addition of External Buffer
        2. 7.7.1.2 GPIO Multiplexed With MMC Interface
        3. 7.7.1.3 Additional Information
        4. 7.7.1.4 GPIO Checklist
      2. 7.7.2 On-Board Hardware Diagnostics
        1. 7.7.2.1 Monitoring of On-board Supply Voltages Using Processor Voltage Monitors
          1. 7.7.2.1.1 Voltage Monitor Inputs Connection When Used
            1. 7.7.2.1.1.1 Voltage Monitor Checklist
          2. 7.7.2.1.2 Voltage Monitor Inputs Connection When Not Used
        2. 7.7.2.2 Internal Temperature Monitoring
          1. 7.7.2.2.1 Internal Temperature Monitoring Checklist
        3. 7.7.2.3 Connection of Error Signal Output (MCU_SAFETY_ERRORn)
        4. 7.7.2.4 High Frequency Oscillator (MCU_OSC0) Clock Loss Detection
          1. 7.7.2.4.1 Crystal or External Oscillator Mal-function
    8. 7.8 EVM or SK Specific Circuit Implementation (Reuse)
    9. 7.9 Performing Board Level Testing During Custom Board Bring-up
      1. 7.9.1 Processor Pin Configuration Using Pinmux Tool
      2. 7.9.2 Schematics Configurations
      3. 7.9.3 Connection of Supply Rails to External Pullups
      4. 7.9.4 Peripheral (Subsystem) Clock Outputs
      5. 7.9.5 General Board Bring-up and Debug
        1. 7.9.5.1 Clock Output for Board Bring-Up, Test or Debug
        2. 7.9.5.2 Additional Information
        3. 7.9.5.3 General Board Bring-up and Debug Checklist
  11. 8 Self-Review of Custom Board Schematic Design
  12. 9 Custom Board Layout Notes (Added Near to the Schematic Sections) and General Guidelines
    1. 9.1 Layout Considerations
  13. 10Custom Board Design Simulation
    1. 10.1 DDR-MARGIN-FW
  14. 11Additional References
    1. 11.1 FAQ Covering AM64x, AM243x, AM62x, AM62Ax, AM62D-Q1, AM62Px, AM62Lx Processor Families
    2. 11.2 FAQs - Processor Product Family Wise and Sitara Processor Families
    3. 11.3 Schematics Review (Self) and Schematic Review Request (Suppliers)
    4. 11.4 Processor Attached Devices Checklist
  15. 12User's Guide Content and Usage Summary
  16. 13References
    1. 13.1 AM64x
    2. 13.2 AM243x
    3. 13.3 Common References
    4. 13.4 Master List of Available FAQs - Processor Family Wise
    5. 13.5 Master List of Available FAQs - Sitara Processor Families
    6. 13.6 FAQs Including Software Related
    7. 13.7 FAQs for Attached Devices
  17.   A Terminology
  18.   Revision History

6.1.1.2 IO Supply for IO Groups

The below FAQ includes recommendations on CAP_VDDSn capacitor value, and the effect of the capacitor assembly (mounted or shorted):

[FAQ] AM625 / AM623 / AM620-Q1 / AM62L / AM62Ax / AM62D-Q1 / AM62Px / AM64x / AM243x Design Recommendations / Custom board hardware design – Queries related to CAP_VDDSx CAP_VDDS

The processor families support x7 (seven) dual-voltage IO supply for IO groups (VDDSHVx [x = 0-5]) and IO supply for IO group MCU (VDDSHV_MCU). Each IO supply for IO group is connected (referenced) to a fixed set of IOs. Each IO supply for IO group can be connected to fixed (VDDSHV5 supports dynamic supply switching) 3.3V or 1.8V supply independently. The IO supply for IO group defines a common operating voltage for the entire set (fixed set) of IOs.

Processor pads (pins) designated as CAP_VDDSn [n = 0-5] and CAP_VDDS_MCU connects the external capacitor to the internal IO supply for IO group regulator when the IO supply for IO groups connect to 3.3V supply (optional when IO supply for IO groups supplies connect to 1.8V). A 1μF (connected between the pins and VSS, see the processor-specific data sheet) capacitor is recommended. See the processor-specific data sheet for the recommended capacitor voltage rating and allowed capacitance range. When IO supply for IO groups are connected to 3.3V, the steady state DC output VDDSHVx/2, is the voltage to be considered for choosing the capacitor voltage rating considering the DC bias effect.

A 3.3μF (recommended tolerance is ± 20%) capacitor is recommended to be connected between the pin CAP_VDDSHV_MMC1 and VSS.

To minimize PCB loop inductance, place the capacitors on the back side of the PCB in the array of the BGA. The choice of capacitor voltage rating influences capacitor package (size) selection.

The recommendation is to select capacitor with ESR < 1Ω, keep the trace loop inductance < 2.5nH.

A number of processor IOs are not fail-safe. For information on available fail-safe IOs, see the processor-specific data sheet. The recommendation is to connect the IO supply of attached devices to the same power source connected to the respective processor dual-voltage IO supply for IO group (VDDSHVx) to make sure the custom board design never applies potential to any of the processor IOs that is not powered. Applying external input to the IOs that are not fail-safe when IO supply for IO groups supply is not available can affect the processor functionality, performance and reliability.

For more information on power-sequencing requirements between the processor and attached devices including signal isolation for fail-safe operation, see the following FAQ:

[FAQ] AM625 / AM623 / AM620-Q1 / AM625-Q1 / AM625SIP : Custom board hardware design – Power sequencing between SOC (Processor) and the Attached devices (Fail-safe)

The FAQ is generic and can also be used for AM64x and AM243x processor families.

Note:

The recommendation is to verify that a valid supply voltage for the VDDSHVx is present before applying input to the associated processor IOs or peripherals.

The recommendation is to connect the VDDSHVx supplies and associated CAP_VDDSn (when IO supply connected is 3.3V, optional for 1.8V) capacitor irrespective of the usage of the processor IOs or peripherals.