General

Review and verify the following for the custom schematic design:

1. Reviewed above "Common checklist for all sections" section of the user's guide.
2. Number of attached devices supported.
3. Connection of address, clock, control and data signals.
4. Connection and routing topology followed based on number of memory devices connected.
5. Connection of signals based on the selected memory size.
6. Differential clock termination.
7. DDR reference voltage resistor divider.
8. Value of the VTT resistors and filter capacitors used for differential clock.
9. VTT Termination for address and control signals when x2 memory devices are used.
10. Connection of DDRSS RESETn signal to DDR_RESETn memory reset input.
11. Connection of ODT signal from DDRSS to memory device (external pull is optional).
12. Connection of Alert, TEN, ZQn and DDR0_CAL0 pins.
13. Swapping of Data bits and data groups.

Schematic Review

Follow the below list for the custom schematic design:

1. x1 16-bit and x2 8-bit are the supported memory configuration.
2. The recommendation is to compare the bulk and decoupling capacitors used and values with EVM schematic implementation.
3. Supply rails connected to the processor DDRSS peripheral supply rail and the attached memory device IO follow the processor and attached memory device ROC.
4. Connection of address, clock, control and data signals, as per the AM64x\AM243x DDR Board Design and Layout Guidelines.
5. Routing topology followed based on number of memory devices connected ((data bus topology is always point-to-point), (x1 16-bit, point-to-point and x2 8-bit, daisy for address and control)).
6. Connection of signals based on the selected memory size (CS0, CS1, BG0, BG1, refer AM64x\AM243x DDR Board Design and Layout Guidelines).
7. Differential clock termination using x2 resistors and filter capacitor. Value of the VTT resistors and filter capacitors used. (Refer EVM schematics).
8. DDR reference voltage resistor divider value and tolerance. Resistor divider connection (1kΩ, ±1%) for DDR reference DDR_VREFCA generation. The recommendation is to place a decoupling capacitor 0.1μF across the resistors and near to the memory pin.
9. VTT Termination for address and control signals when x2 memory devices are used (optional for x1 memory device) and VTT termination supply (LDO) implementation. VTT LDO implementation. VTT resistors and capacitors (1 capacitor for every 2 VTT resistors) quantity and value (The recommendation is to follow TMDS64EVM).
10. Connection of DDRSS RESETn signal to DDR_RESETn memory reset input (to hold the signal low during power-on initialization). The recommendation is to add a pulldown (10kΩ) for DDRSS RESETn signal and placed near the memory device reset input pin.
11. Connection of Alert (10kΩ pullup) and TEN (1kΩ pulldown) signals.
12. ZQ0, ZQ1, Memory device IO calibration resistor (240Ω, ±1%) connection across ZQ and VSS.
13. DDR0_CAL0, DDRSS IO pad calibration resistor (240Ω, ±1%) connected across DDR0_CAL0 and VSS.
14. Connection of ODT signal from DDRSS to memory device (external pull is optional).
15. Follow AM64x\AM243x DDR Board Design and Layout Guidelines when data bits and data groups are swapped.

Additional

1. The recommendation is to refer TMDS64EVM for implementing VTT terminations for DDR4 address and control signals and VTT supply (LDO).
2. The recommendation is to add layout notes on the schematic (the recommendation is to follow the AM64x\AM243x DDR Board Design and Layout Guidelines).
3. The recommendation is to follow the Pin Connectivity Requirements section of the processor-specific data sheet for connecting unused DDRSS interface signals.
4. Connection of required DDRSS signals to the memory device for expansion.