General
Review and verify the following for
the custom schematic design:
- Reviewed above "Common checklist for all sections" section of the
user's guide
- Connection of the PCIe interface
signals
- Connection of the required filters and decoupling capacitors (Follow the EVM
implementation)
- Clock termination and connections
- Connection of recommended terminations
- Provisioning for AC-coupling capacitors as per recommendation
- ANDing logic is used for implementing the processor or attached device reset
- Connection of other PCIe interface signals
- Connection of SERDES0_REXT resistor including value and tolerance
- Resetting the PCIe add-on card reset
Schematic Review
Follow the below list for the custom
schematic design:
- Connection of the transmit, receive and clock signals as per the required
PCIe configuration
- In case the design uses external clock, the clock can be connect to a PCIe
compliant 100MHz differential clock
- In case the internal processor clock is being used as output, 50Ω (49.9Ω) to
GND resistors are recommended to be placed near processor for both CLKP/CLKN
signals
- Check latest documentation to determine if output clock is PCIe compliant
- SERDES0_TX0_P and
SERDES0_TX0_N signals are configured as PCIE0_TX0_P and PCIE0_TX0_N.
SERDES0_RX0_P and SERDES0_RX0_N signals are configured as PCIE0_RX0_P and
PCIE0_RX0_N. The recommendation is to connect a resistor (pulldown) for
SERDES0_REXT (close to processor pin). Refer processor-specific data sheet
for resistor value and tolerance.
- AC-coupling capacitors are recommended for PCIe transmit and receive pairs.
The capacitors are recommended to be placed close to the PCIe
transmitter.
- In case a PCIe connector is
used in the design (off board), the recommendation is to connect the receive
pair directly to the connector (no DC-blocking capacitors). The DC-blocking
capacitors for the receive pair is (expected to be) present on the far-end
PCIe device.
- Implementation of processor or attached device reset through PCIe interface
connector. The recommendation is to implement the attached PCIe device
(add-on card) reset using a 2-input ANDing logic. Processor GPIO is
connected as one of the input to the AND gate with provision for pullup
(10kΩ or 47kΩ) (to support boot) near to the ANDing logic AND gate input and
provision for 0Ω to isolate the GPIO output for testing or debug. The other
input to the AND gate is the MAIN domain warm reset status output
(RESETSTATz).
Additional
- With processor silicon PG2.0,
AM64x can source the PCIE ref clock but it does not support SSC when sourcing
the PCIE ref clock. Validation was performed using common clock topology (i.e,
Root-complex and End-point using the same clock). So both ends using the same
clock as sourced from AM64x PCIE ref clock but NO SSC = OK. Both ends using same
clock as sourced from external source both Yes or No SSC = OK. Using independent
clock sources for Root-complex and End-point = not validated topology
- PCIe interface signals are not
fail-safe.
- There is no support for PCIe
swing tuning.
- See the TMDS64EVM and AM64x
evaluation module for Sitara processors for PCIe implementation reference
- See the Jacinto7/Sitara
High-Speed Interface Layout Guidelines (available on TI.com) for
detailed recommendations for proper PCIe SERDES signal connections and routing.
The recommendation is to add appropriate constraints or routing requirements to
your schematic