3 CMOS Wear Out Mechanisms and IC Design

The current generation of TI industrial grade embedded processor products is designed to support a useful lifetime of 10 year operating at 105°C junction temperature T_J.

The 10 year lifetime assumes a worst case situation of 100% powered on and run at a constant 105°C T_J temperature.

TI EP products are designed for reliability so that the onset of the wear out mechanisms occurs beyond the useful life period. This is illustrated in Figure 1.

Robustness to prominent silicon wear-out mechanisms that are designed for include:

• Gate oxide integrity (GOI)
• Electro-migration (EM)
• Time dependent di-electric breakdown (TDDB)

In addition, mechanisms that cause parametric shift over lifetime, such as Negative Bias Temperature Instability (NBTI) and Channel Hot Carriers (CHC), are also considered within the product design.

For most silicon technologies, the critical wear out mechanism is EM.