SPRUJ53 April 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
Table 3-104 lists the memory-mapped registers for the DEV_CFG_REGS registers. All register offset addresses not listed in Table 3-104 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
8h | PARTIDL | Lower 32-bit of Device PART Identification Number | Go | |
Ah | PARTIDH | Upper 32-bit of Device PART Identification Number | Go | |
Ch | REVID | Device Revision Number | Go | |
74h | TRIMERRSTS | TRIM Error Status register | Go | |
82h | SOFTPRES0 | Processing Block Software Reset register | EALLOW | Go |
86h | SOFTPRES2 | EPWM Software Reset register | EALLOW | Go |
88h | SOFTPRES3 | ECAP Software Reset register | EALLOW | Go |
8Ah | SOFTPRES4 | EQEP Software Reset register | EALLOW | Go |
90h | SOFTPRES7 | SCI Software Reset register | EALLOW | Go |
92h | SOFTPRES8 | SPI Software Reset register | EALLOW | Go |
94h | SOFTPRES9 | I2C Software Reset register | EALLOW | Go |
96h | SOFTPRES10 | CAN Software Reset register | EALLOW | Go |
98h | SOFTPRES11 | McBSP/USB Software Reset register | EALLOW | Go |
9Ch | SOFTPRES13 | ADC Software Reset register | EALLOW | Go |
9Eh | SOFTPRES14 | CMPSS Software Reset register | EALLOW | Go |
A0h | SOFTPRES15 | PGA Software Reset register | EALLOW | Go |
A2h | SOFTPRES16 | DAC Software Reset register | EALLOW | Go |
A4h | SOFTPRES17 | CLB Software Reset register | EALLOW | Go |
A6h | SOFTPRES18 | FSI Software Reset register | EALLOW | Go |
A8h | SOFTPRES19 | LIN Software Reset register | EALLOW | Go |
AAh | SOFTPRES20 | PMBUS Software Reset register | EALLOW | Go |
ACh | SOFTPRES21 | DCC Software Reset register | EALLOW | Go |
B6h | SOFTPRES26 | AES Software Reset register | EALLOW | Go |
B8h | SOFTPRES27 | EPG Software Reset register | EALLOW | Go |
BAh | SOFTPRES28 | Flash Software Reset register | EALLOW | Go |
BEh | SOFTPRES30 | NNPU Software reset register | EALLOW | Go |
130h | TAP_STATUS | Status of JTAG State machine & Debugger Connect | Go | |
132h | TAP_CONTROL | Disable TAP control | Go | |
19Ah | USBTYPE | Configures USB Type for the device | EALLOW | Go |
19Bh | ECAPTYPE | Configures ECAP Type for the device | EALLOW | Go |
1A6h | MCUCNF3 | MCU Configuration: ETPWM | Go | |
1B0h | MCUCNF8 | MCU Configuration: SCI | Go | |
1B6h | MCUCNF11 | MCU Configuration: CAN | Go | |
1B8h | MCUCNF12 | MCU Configuration: McBSP_USB | Go | |
1BCh | MCUCNF14 | MCU Configuration: ADC | Go | |
1C0h | MCUCNF16 | MCU Configuration: PGA | Go | |
1C4h | MCUCNF18 | MCU Configuration: Lx.1 SRAM Customization | Go | |
1C8h | MCUCNF20 | MCU Configuration: GSx SRAM Customization | Go | |
1CAh | MCUCNF21 | MCU Configuration: CLB | Go | |
1CEh | MCUCNF23 | MCU Configuration: LIN | Go | |
1DEh | MCUCNF31 | MCU Configuration: Flash Bank0 | Go | |
1E0h | MCUCNF32 | MCU Configuration: Flash Bank1 | Go | |
1E2h | MCUCNF33 | MCU Configuration: Flash Bank2 | Go | |
1E4h | MCUCNF34 | MCU Configuration: Flash Bank3 | Go | |
1E6h | MCUCNF35 | MCU Configuration: Flash Bank4 | Go | |
1F8h | MCUCNFLOCK | Lock bit for MCUCNFx registers | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-105 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1C | W 1C | Write 1 to clear |
W1S | W 1S | Write 1 to set |
WOnce | W Once | Write Write once |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
PARTIDL is shown in Figure 3-85 and described in Table 3-106.
Return to the Summary Table.
Lower 32-bit of Device PART Identification Number
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | ||||||
R-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FLASH_SIZE | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | INSTASPIN | RESERVED | RESERVED | PIN_COUNT | |||
R-0h | R-X | R-0h | R-X | R-X | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
QUAL | RESERVED | RESERVED | RESERVED | ||||
R-X | R-0h | R-0h | R-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | 0h | Reserved |
27-24 | RESERVED | R | 0h | Reserved |
23-16 | FLASH_SIZE | R | X | 0x8 - 1088KB 0x7 - 1024KB 0x6 - 576KB 0x5 - 512KB 0x4 - 256KB 0x3 -128KB 0x0-0x2 - Reserved Reset type: PORESETn |
15 | RESERVED | R | 0h | Reserved |
14-13 | INSTASPIN | R | X | 1 = InstaSPIN-FOC 2 = NONE 3 = NONE Reset type: PORESETn |
12 | RESERVED | R | 0h | Reserved |
11 | RESERVED | R | X | Reserved |
10-8 | PIN_COUNT | R | X | 0 = 56 pin QFN 1 = 64 pin QFP 2 = 80 pin QFP 3 = 100 pin QFP 4 = 128 pin QFP 5 = Reserved 6 = Reserved 7 = Reserved Reset type: PORESETn |
7-6 | QUAL | R | X | 0 = Engineering sample (TMX) 1 = Pilot production (TMP) 2 = Fully qualified (TMS) Reset type: PORESETn |
5 | RESERVED | R | 0h | Reserved |
4-3 | RESERVED | R | 0h | Reserved |
2-0 | RESERVED | R | 0h | Reserved |
PARTIDH is shown in Figure 3-86 and described in Table 3-107.
Return to the Summary Table.
Upper 32-bit of Device PART Identification Number
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DEVICE_CLASS_ID | PARTNO | ||||||||||||||
R-9h | R-X | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FAMILY | RESERVED | RESERVED | |||||||||||||
R-5h | R-0h | R-0h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | DEVICE_CLASS_ID | R | 9h | Device class ID Reset type: PORESETn |
23-16 | PARTNO | R | X | Refer to Datasheet for Device Part Number Reset type: PORESETn |
15-8 | FAMILY | R | 5h | Device Family Reset type: PORESETn |
7-4 | RESERVED | R | 0h | Reserved |
3-0 | RESERVED | R | 0h | Reserved |
REVID is shown in Figure 3-87 and described in Table 3-108.
Return to the Summary Table.
Device Revision Number
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVID_EXT | REVID | ||||||||||||||
R-0h | R/WOnce-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-8 | REVID_EXT | R | 0h | Device Revision ID extension. Reset type: XRSn |
7-0 | REVID | R/WOnce | 0h | Device Revision ID. Loaded from flash trim sector by boot rom. Reset value is die-specific. Reset type: XRSn |
TRIMERRSTS is shown in Figure 3-88 and described in Table 3-109.
Return to the Summary Table.
TRIM Error Status register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LERR | ||||||||||||||||||||||||||||||
R-0-0h | R/WSonce-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-0 | LERR | R/WSonce | 0h | TRIM information load error status. This will include error during SRAM repair also. 00000: No error during load Other: Non zero value indicates error during load Note: [1] This bit is updated by software. Details will be filled in once the Boot ROM related requirements are complete. It should have bits to indicate (i) Double bit error during trim load (ii) Single bit error during trim load (iii) Double bit error during SRAM repair load (iv) Single bit error error during SRAM repair load (v) SRAM repair error load (chain is broken) (vi) PWRUPSTS.TRIMOVER signal is not asserted even after the full wait time Reset type: XRSn |
SOFTPRES0 is shown in Figure 3-89 and described in Table 3-110.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | CPU1_ERAD | ||||||
R-0-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R-0-0h | R/W-0h | R/W-0h | R-0-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | CPU1_CLA1 | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R-0 | 0h | Reserved |
24 | CPU1_ERAD | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
23-16 | RESERVED | R-0 | 0h | Reserved |
15 | RESERVED | R-0 | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | CPU1_CLA1 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES2 is shown in Figure 3-90 and described in Table 3-111.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | EPWM12 | EPWM11 | EPWM10 | EPWM9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPWM8 | EPWM7 | EPWM6 | EPWM5 | EPWM4 | EPWM3 | EPWM2 | EPWM1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15 | RESERVED | R/W | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12 | RESERVED | R/W | 0h | Reserved |
11 | EPWM12 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
10 | EPWM11 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
9 | EPWM10 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
8 | EPWM9 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
7 | EPWM8 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
6 | EPWM7 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
5 | EPWM6 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
4 | EPWM5 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
3 | EPWM4 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
2 | EPWM3 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
1 | EPWM2 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | EPWM1 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES3 is shown in Figure 3-91 and described in Table 3-112.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | ECAP2 | ECAP1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | ECAP2 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | ECAP1 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES4 is shown in Figure 3-92 and described in Table 3-113.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | EQEP3 | EQEP2 | EQEP1 | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | EQEP3 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
1 | EQEP2 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Note: This bit is applicable only for Topoauto Reset type: SYSRSn |
0 | EQEP1 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES7 is shown in Figure 3-93 and described in Table 3-114.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | SCI_C | SCI_B | SCI_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | SCI_C | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
1 | SCI_B | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | SCI_A | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES8 is shown in Figure 3-94 and described in Table 3-115.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | SPI_B | SPI_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R-0 | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | SPI_B | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | SPI_A | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES9 is shown in Figure 3-95 and described in Table 3-116.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | I2C_B | I2C_A | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R-0 | 0h | Reserved |
1 | I2C_B | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | I2C_A | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES10 is shown in Figure 3-96 and described in Table 3-117.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | MCAN_B | MCAN_A | RESERVED | RESERVED | RESERVED | RESERVED |
R-X | R-X | R-X | R-X | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | RESERVED | R | X | Reserved |
6 | RESERVED | R | X | Reserved |
5 | MCAN_B | R | X | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
4 | MCAN_A | R | X | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Note: This bit is applicable only for Topoauto Reset type: SYSRSn |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | RESERVED | R/W | 0h | Reserved |
SOFTPRES11 is shown in Figure 3-97 and described in Table 3-118.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | USB_A | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R-0 | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | USB_A | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
15-2 | RESERVED | R-0 | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | RESERVED | R/W | 0h | Reserved |
SOFTPRES13 is shown in Figure 3-98 and described in Table 3-119.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADC_E | ADC_D | ADC_C | ADC_B | ADC_A | ||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R-0 | 0h | Reserved |
4 | ADC_E | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
3 | ADC_D | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
2 | ADC_C | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
1 | ADC_B | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | ADC_A | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES14 is shown in Figure 3-99 and described in Table 3-120.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | CMPSS4 | CMPSS3 | CMPSS2 | CMPSS1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | CMPSS4 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
2 | CMPSS3 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
1 | CMPSS2 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | CMPSS1 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES15 is shown in Figure 3-100 and described in Table 3-121.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | PGA3 | PGA2 | PGA1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | PGA3 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
1 | PGA2 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | PGA1 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES16 is shown in Figure 3-101 and described in Table 3-122.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | DAC_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R-0 | 0h | Reserved |
19 | RESERVED | R/W | 0h | Reserved |
18 | RESERVED | R/W | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | DAC_A | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
15-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | RESERVED | R/W | 0h | Reserved |
SOFTPRES17 is shown in Figure 3-102 and described in Table 3-123.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | CLB2 | CLB1 | |||
R-0h | R/W-0h | R/W-0h | R-X | R-X | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | CLB2 | R | X | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | CLB1 | R | X | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES18 is shown in Figure 3-103 and described in Table 3-124.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | FSIRX_A | FSITX_A | |||
R-0h | R/W-0h | R/W-0h | R-X | R-X | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | FSIRX_A | R | X | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | FSITX_A | R | X | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES19 is shown in Figure 3-104 and described in Table 3-125.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | LIN_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | LIN_A | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Note: This bit is applicable only for Topoauto Reset type: SYSRSn |
SOFTPRES20 is shown in Figure 3-105 and described in Table 3-126.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | PMBUS_A | |||||
R-0h | R-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | RESERVED | R | 0h | Reserved |
0 | PMBUS_A | R | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES21 is shown in Figure 3-106 and described in Table 3-127.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DCC1 | DCC0 | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R-0 | 0h | Reserved |
1 | DCC1 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | DCC0 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES26 is shown in Figure 3-107 and described in Table 3-128.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AESA | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R-0 | 0h | Reserved |
0 | AESA | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES27 is shown in Figure 3-108 and described in Table 3-129.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EPG1 | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R-0 | 0h | Reserved |
0 | EPG1 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES28 is shown in Figure 3-109 and described in Table 3-130.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FLASHA | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R-0 | 0h | Reserved |
0 | FLASHA | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Note: Whenever the reset to flash is asserted, it will be internally stretched to ~15us Reset type: SYSRSn |
SOFTPRES30 is shown in Figure 3-110 and described in Table 3-131.
Return to the Summary Table.
NNPU Software reset register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NNPU | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R-0 | 0h | Reserved |
0 | NNPU | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
TAP_STATUS is shown in Figure 3-111 and described in Table 3-132.
Return to the Summary Table.
Status of JTAG State machine & Debugger Connect
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DCON | RESERVED | ||||||
R-0h | R-0-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TAP_STATE | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TAP_STATE | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | DCON | R | 0h | DebugConnect indication from IcePick. Reset type: PORESETn |
30-16 | RESERVED | R-0 | 0h | Reserved |
15-0 | TAP_STATE | R | 0h | TAP State Vector. With bits representing, Connect coresponding POTAP* output to the 0:TLR, 1:IDLE, 2:SELECTDR, 3:CAPDR, 4:SHIFTDR, 5:EXIT1DR, 6:PAUSEDR, 7:EXIT2DR, 8:UPDTDR, 9:SLECTIR, 10:CAPIR, 11:SHIFTIR, 12:EXIT1IR, 13:PAUSEIR, 14:EXIT2IR, 15:UPDTIR, Reset type: PORESETn |
TAP_CONTROL is shown in Figure 3-112 and described in Table 3-133.
Return to the Summary Table.
Disable TAP control
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R-0/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BSCAN_DIS | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY, only 32-bit writes will succeed (provided the KEY matches). 16-bit writes to the upper or lower half of this register will be ignored Reset type: PORESETn |
15-1 | RESERVED | R-0 | 0h | Reserved |
0 | BSCAN_DIS | R/W | 0h | Disables BSCAN TAP control : 0: BSCAN TAP control enabled 1: BSCAN TAP control disabled Reset type: PORESETn |
USBTYPE is shown in Figure 3-113 and described in Table 3-134.
Return to the Summary Table.
Based on the configuration enables disables features associated with the USB type.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
LOCK | RESERVED | ||||||
R/WSonce-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TYPE | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | LOCK | R/WSonce | 0h | 1: Write to this register is not allowed. 0: Write to this register is allowed. Reset type: CPU1.SYSRSn |
14-2 | RESERVED | R-0 | 0h | Reserved |
1-0 | TYPE | R/W | 0h | '00,10,11' : 1. Global interrupt feature is not enabled, interrupts fired unconditionally. '01' : 1.Global interrupt feature is enabled, refer to the spec doc for more details about global interrupt feature. Reset type: CPU1.SYSRSn |
ECAPTYPE is shown in Figure 3-114 and described in Table 3-135.
Return to the Summary Table.
Based on the configuration enables disables features associated with the ECAP type.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
LOCK | RESERVED | ||||||
R/WSonce-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TYPE | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | LOCK | R/WSonce | 0h | 1: Write to this register is not allowed. 0: Write to this register is allowed. Reset type: SYSRSn |
14-2 | RESERVED | R-0 | 0h | Reserved |
1-0 | TYPE | R/W | 0h | '00,10,11' : 1. No EALLOW protection to ECAP registers. '01' : 1. ECAP registers are EALLOW protected. Reset type: SYSRSn |
MCUCNF3 is shown in Figure 3-115 and described in Table 3-136.
Return to the Summary Table.
MCU Configuration: ETPWM
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | EPWM12 | EPWM11 | EPWM10 | EPWM9 |
R-X | R-X | R-X | R-X | R-X | R-X | R-X | R-X |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPWM8 | EPWM7 | EPWM6 | EPWM5 | EPWM4 | EPWM3 | EPWM2 | EPWM1 |
R-X | R-X | R-X | R-X | R-X | R-X | R-X | R-X |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15 | RESERVED | R | X | Reserved |
14 | RESERVED | R | X | Reserved |
13 | RESERVED | R | X | Reserved |
12 | RESERVED | R | X | Reserved |
11 | EPWM12 | R | X | EPWM12 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
10 | EPWM11 | R | X | EPWM11 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
9 | EPWM10 | R | X | EPWM10 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
8 | EPWM9 | R | X | EPWM9 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
7 | EPWM8 | R | X | EPWM8 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
6 | EPWM7 | R | X | EPWM7 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
5 | EPWM6 | R | X | EPWM6 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
4 | EPWM5 | R | X | EPWM5 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
3 | EPWM4 | R | X | EPWM4 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
2 | EPWM3 | R | X | EPWM3 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
1 | EPWM2 | R | X | EPWM2 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
0 | EPWM1 | R | X | EPWM1 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
MCUCNF8 is shown in Figure 3-116 and described in Table 3-137.
Return to the Summary Table.
MCU Configuration: SCI
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | SCI_C | SCI_B | SCI_A | |||
R-0-0h | R-X | R-X | R-X | R-X | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R | X | Reserved |
2 | SCI_C | R | X | SCI_C : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
1 | SCI_B | R | X | SCI_B : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
0 | SCI_A | R | X | SCI_A : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
MCUCNF11 is shown in Figure 3-117 and described in Table 3-138.
Return to the Summary Table.
MCU Configuration: CAN
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | MCAN_B | MCAN_A | RESERVED | RESERVED | RESERVED | RESERVED |
R-X | R-X | R-X | R-X | R-X | R-X | R-X | R-X |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | RESERVED | R | X | Reserved |
6 | RESERVED | R | X | Reserved |
5 | MCAN_B | R | X | MCAN_B : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
4 | MCAN_A | R | X | MCAN_A : 0: Feature not present on the device 1: Feature present on the device Note: This bit is applicable only for Topoauto Reset type: PORESETn |
3 | RESERVED | R | X | Reserved |
2 | RESERVED | R | X | Reserved |
1 | RESERVED | R | X | Reserved |
0 | RESERVED | R | X | Reserved |
MCUCNF12 is shown in Figure 3-118 and described in Table 3-139.
Return to the Summary Table.
MCU Configuration: McBSP_USB
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | USB_A | ||||
R-0-0h | R-X | R-0-0h | R-X | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | |||||
R-0-0h | R-X | R-X | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R-0 | 0h | Reserved |
18 | RESERVED | R | X | Reserved |
17 | RESERVED | R-0 | 0h | Reserved |
16 | USB_A | R | X | USB_A : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
15-2 | RESERVED | R-0 | 0h | Reserved |
1 | RESERVED | R | X | Reserved |
0 | RESERVED | R | X | Reserved |
MCUCNF14 is shown in Figure 3-119 and described in Table 3-140.
Return to the Summary Table.
MCU Configuration: ADC
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADC_E | ADC_D | ADC_C | ADC_B | ADC_A | ||
R-0-0h | R-X | R-X | R-X | R-X | R-X | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-5 | RESERVED | R-0 | 0h | Reserved |
4 | ADC_E | R | X | ADC_E : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
3 | ADC_D | R | X | ADC_D : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
2 | ADC_C | R | X | ADC_C : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
1 | ADC_B | R | X | ADC_B : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
0 | ADC_A | R | X | ADC_A : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
MCUCNF16 is shown in Figure 3-120 and described in Table 3-141.
Return to the Summary Table.
MCU Configuration: PGA
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | PGA3 | PGA2 | PGA1 |
R-X | R-X | R-X | R-X | R-X | R-X | R-X | R-X |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | RESERVED | R | X | Reserved |
6 | RESERVED | R | X | Reserved |
5 | RESERVED | R | X | Reserved |
4 | RESERVED | R | X | Reserved |
3 | RESERVED | R | X | Reserved |
2 | PGA3 | R | X | PGA3 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
1 | PGA2 | R | X | PGA2 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
0 | PGA1 | R | X | PGA1 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
MCUCNF18 is shown in Figure 3-121 and described in Table 3-142.
Return to the Summary Table.
MCU Configuration: Lx.1 SRAM Customization
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | LS9_1 | LS8_1 | |||||
R-0-0h | R-X | R-X | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LS7_1 | LS6_1 | LS5_1 | LS4_1 | LS3_1 | LS2_1 | LS1_1 | LS0_1 |
R-X | R-X | R-X | R-X | R-X | R-X | R-X | R-X |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R-0 | 0h | Reserved |
9 | LS9_1 | R | X | LS9_1 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
8 | LS8_1 | R | X | LS8_1 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
7 | LS7_1 | R | X | LS7_1 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
6 | LS6_1 | R | X | LS6_1 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
5 | LS5_1 | R | X | LS5_1 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
4 | LS4_1 | R | X | LS4_1 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
3 | LS3_1 | R | X | LS3_1 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
2 | LS2_1 | R | X | LS2_1 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
1 | LS1_1 | R | X | LS1_1 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
0 | LS0_1 | R | X | LS0_1 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
MCUCNF20 is shown in Figure 3-122 and described in Table 3-143.
Return to the Summary Table.
MCU Configuration: GSx SRAM Customization
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R-X | R-X | R-X | R-X | R-X | R-X | R-X | R-X |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | GS3 | GS2 | GS1 | GS0 |
R-X | R-X | R-X | R-X | R-X | R-X | R-X | R-X |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15 | RESERVED | R | X | Reserved |
14 | RESERVED | R | X | Reserved |
13 | RESERVED | R | X | Reserved |
12 | RESERVED | R | X | Reserved |
11 | RESERVED | R | X | Reserved |
10 | RESERVED | R | X | Reserved |
9 | RESERVED | R | X | Reserved |
8 | RESERVED | R | X | Reserved |
7 | RESERVED | R | X | Reserved |
6 | RESERVED | R | X | Reserved |
5 | RESERVED | R | X | Reserved |
4 | RESERVED | R | X | Reserved |
3 | GS3 | R | X | GS3 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
2 | GS2 | R | X | GS2 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
1 | GS1 | R | X | GS1 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
0 | GS0 | R | X | GS0 : 0: Feature not present on the device 1: Feature present on the device Note: This applies to upper 8KB of GS0 only. Lower 8KB is always available and not affected by this bit value. Reset type: PORESETn |
MCUCNF21 is shown in Figure 3-123 and described in Table 3-144.
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MCU Configuration: CLB
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | CLB2 | CLB1 | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R | 0h | Reserved |
2 | RESERVED | R | 0h | Reserved |
1 | CLB2 | R | 0h | CLB2 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
0 | CLB1 | R | 0h | CLB1 : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
MCUCNF23 is shown in Figure 3-124 and described in Table 3-145.
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MCU Configuration: LIN
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | LIN_A | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R | 0h | Reserved |
2 | RESERVED | R | 0h | Reserved |
1 | RESERVED | R | 0h | Reserved |
0 | LIN_A | R | 0h | LIN_A : 0: Feature not present on the device 1: Feature present on the device Reset type: PORESETn |
MCUCNF31 is shown in Figure 3-125 and described in Table 3-146.
Return to the Summary Table.
MCU Configuration: Flash Bank0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SECT127_112 | SECT111_96 | SECT95_80 | SECT79_64 | SECT63_48 | SECT47_32 | SECT31_16 | SECT15_0 |
R-X | R-X | R-X | R-X | R-X | R-X | R-X | R-X |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | SECT127_112 | R | X | Flash Bank-0: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
6 | SECT111_96 | R | X | Flash Bank-0: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
5 | SECT95_80 | R | X | Flash Bank-0: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
4 | SECT79_64 | R | X | Flash Bank-0: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
3 | SECT63_48 | R | X | Flash Bank-0: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
2 | SECT47_32 | R | X | Flash Bank-0: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
1 | SECT31_16 | R | X | Flash Bank-0: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
0 | SECT15_0 | R | X | Flash Bank-0: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
MCUCNF32 is shown in Figure 3-126 and described in Table 3-147.
Return to the Summary Table.
MCU Configuration: Flash Bank1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SECT127_112 | SECT111_96 | SECT95_80 | SECT79_64 | SECT63_48 | SECT47_32 | SECT31_16 | SECT15_0 |
R-X | R-X | R-X | R-X | R-X | R-X | R-X | R-X |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | SECT127_112 | R | X | Flash Bank-1: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
6 | SECT111_96 | R | X | Flash Bank-1: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
5 | SECT95_80 | R | X | Flash Bank-1: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
4 | SECT79_64 | R | X | Flash Bank-1: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
3 | SECT63_48 | R | X | Flash Bank-1: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
2 | SECT47_32 | R | X | Flash Bank-1: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
1 | SECT31_16 | R | X | Flash Bank-1: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
0 | SECT15_0 | R | X | Flash Bank-1: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
MCUCNF33 is shown in Figure 3-127 and described in Table 3-148.
Return to the Summary Table.
MCU Configuration: Flash Bank2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SECT127_112 | SECT111_96 | SECT95_80 | SECT79_64 | SECT63_48 | SECT47_32 | SECT31_16 | SECT15_0 |
R-X | R-X | R-X | R-X | R-X | R-X | R-X | R-X |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | SECT127_112 | R | X | Flash Bank-2: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
6 | SECT111_96 | R | X | Flash Bank-2: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
5 | SECT95_80 | R | X | Flash Bank-2: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
4 | SECT79_64 | R | X | Flash Bank-2: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
3 | SECT63_48 | R | X | Flash Bank-2: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
2 | SECT47_32 | R | X | Flash Bank-2: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
1 | SECT31_16 | R | X | Flash Bank-2: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
0 | SECT15_0 | R | X | Flash Bank-2: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
MCUCNF34 is shown in Figure 3-128 and described in Table 3-149.
Return to the Summary Table.
MCU Configuration: Flash Bank3
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SECT127_112 | SECT111_96 | SECT95_80 | SECT79_64 | SECT63_48 | SECT47_32 | SECT31_16 | SECT15_0 |
R-X | R-X | R-X | R-X | R-X | R-X | R-X | R-X |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | SECT127_112 | R | X | Flash Bank-3: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
6 | SECT111_96 | R | X | Flash Bank-3: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
5 | SECT95_80 | R | X | Flash Bank-3: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
4 | SECT79_64 | R | X | Flash Bank-3: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
3 | SECT63_48 | R | X | Flash Bank-3: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
2 | SECT47_32 | R | X | Flash Bank-3: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
1 | SECT31_16 | R | X | Flash Bank-3: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
0 | SECT15_0 | R | X | Flash Bank-3: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
MCUCNF35 is shown in Figure 3-129 and described in Table 3-150.
Return to the Summary Table.
MCU Configuration: Flash Bank4
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | SECT31_16 | SECT15_0 |
R-X | R-X | R-X | R-X | R-X | R-X | R-X | R-X |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | RESERVED | R | X | Reserved |
6 | RESERVED | R | X | Reserved |
5 | RESERVED | R | X | Reserved |
4 | RESERVED | R | X | Reserved |
3 | RESERVED | R | X | Reserved |
2 | RESERVED | R | X | Reserved |
1 | SECT31_16 | R | X | Flash Bank-4: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
0 | SECT15_0 | R | X | Flash Bank-4: 0: Respective sectors are not present in the device 1: Respective sectors are present in the device Reset type: PORESETn |
MCUCNFLOCK is shown in Figure 3-130 and described in Table 3-151.
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Lock bit for MCUCNFx registers
The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed
Note:
Any SOnce bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MCUCNFLOCK | ||||||
R-0-0h | R/WSonce-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R-0 | 0h | Reserved |
0 | MCUCNFLOCK | R/WSonce | 0h | Lock bit for all MCUCNF registers: 0: Registers are not locked 1: Register are locked Reset type: CPU1.SYSRSn |