Product details

Illumination wavelength (Min) (nm) 400 Illumination wavelength (Max) (nm) 700 Micromirror array size 1920 x 1080 Chipset family DLP9500, DLPC410, DLPR410, DLPA200, DLPLCR95EVM, DLPLCRC410EVM Micromirror pitch (um) 10.8 Component type DMD Micromirror array orientation Orthogonal Pattern rate, binary (Max) (Hz) 23148 Array diagonal (in) 0.95 Display resolution (Max) 1920 x 1080 (1080p) Pattern rate, 8-bit (Max) (Hz) 2893 Micromirror driver support External Thermal dissipation (°C/W) 0.5
Illumination wavelength (Min) (nm) 400 Illumination wavelength (Max) (nm) 700 Micromirror array size 1920 x 1080 Chipset family DLP9500, DLPC410, DLPR410, DLPA200, DLPLCR95EVM, DLPLCRC410EVM Micromirror pitch (um) 10.8 Component type DMD Micromirror array orientation Orthogonal Pattern rate, binary (Max) (Hz) 23148 Array diagonal (in) 0.95 Display resolution (Max) 1920 x 1080 (1080p) Pattern rate, 8-bit (Max) (Hz) 2893 Micromirror driver support External Thermal dissipation (°C/W) 0.5
CLGA (FLN) 355 1777 mm² 42.16 x 42.16
  • 0.95-Inch Diagonal Micromirror Array
    • 1920 × 1080 Array of Aluminum, Micrometer-Sized Mirrors (1080p Resolution)
    • 10.8-µm Micromirror Pitch
    • ±12° Micromirror Tilt Angle (Relative to Flat State)
    • Designed for Corner Illumination
  • Designed for Use with Visible Light
    (400 to 700 nm):
    • Window Transmission 96% (Single Pass, Through Two Window Surfaces)
    • Micromirror Reflectivity 89%
    • Array Diffraction Efficiency 87%
    • Array Fill Factor 94%
  • Four 16-Bit, Low-Voltage Differential Signaling (LVDS), Double Data Rate (DDR) Input Data Buses
  • Up to 400-MHz Input Data Clock Rate
  • 42.2-mm × 42.2-mm × 7-mm Package Footprint
  • Hermetic Package
  • 0.95-Inch Diagonal Micromirror Array
    • 1920 × 1080 Array of Aluminum, Micrometer-Sized Mirrors (1080p Resolution)
    • 10.8-µm Micromirror Pitch
    • ±12° Micromirror Tilt Angle (Relative to Flat State)
    • Designed for Corner Illumination
  • Designed for Use with Visible Light
    (400 to 700 nm):
    • Window Transmission 96% (Single Pass, Through Two Window Surfaces)
    • Micromirror Reflectivity 89%
    • Array Diffraction Efficiency 87%
    • Array Fill Factor 94%
  • Four 16-Bit, Low-Voltage Differential Signaling (LVDS), Double Data Rate (DDR) Input Data Buses
  • Up to 400-MHz Input Data Clock Rate
  • 42.2-mm × 42.2-mm × 7-mm Package Footprint
  • Hermetic Package

The DLP9500 1080p chipset is part of the DLP® Discovery™ 4100 platform, which enables high resolution and high performance spatial light modulation. The DLP9500 is the digital micromirror device (DMD) fundamental to the 0.95 1080p chipset. The DLP Discovery 4100 platform also provides the highest level of individual micromirror control with the option for random row addressing. Combined with a hermetic package, the unique capability and value offered by DLP9500 makes it well suited to support a wide variety of industrial, medical, and advanced display applications.

In addition to the DLP9500 DMD, the 0.95 1080p chipset includes a dedicated DLPC410 controller required for high speed pattern rates of 23,148 Hz (1-bit binary) and 2,893 Hz (8-bit gray), one unit DLPR410 (DLP Discovery 4100 Configuration PROM), and two units DLPA200 (DMD micromirror drivers).

Reliable function and operation of the DLP9500 requires that it be used in conjunction with the other components of the chipset. A dedicated chipset provides developers easier access to the DMD as well as high speed, independent micromirror control.

DLP9500 is a digitally controlled micro-electromechanical system (MEMS) spatial light modulator (SLM). When coupled to an appropriate optical system, the DLP9500 can be used to modulate the amplitude, direction, and/or phase of incoming light.

Electrically, the DLP9500 consists of a two-dimensional array of 1-bit CMOS memory cells, organized in a grid of 1920 memory cell columns by 1080 memory cell rows. The CMOS memory array is addressed on a row-by-row basis, over four 16-bit LVDS DDR buses. Addressing is handled by a serial control bus. The specific CMOS memory access protocol is handled by the DLPC410 digital controller.

The DLP9500 1080p chipset is part of the DLP® Discovery™ 4100 platform, which enables high resolution and high performance spatial light modulation. The DLP9500 is the digital micromirror device (DMD) fundamental to the 0.95 1080p chipset. The DLP Discovery 4100 platform also provides the highest level of individual micromirror control with the option for random row addressing. Combined with a hermetic package, the unique capability and value offered by DLP9500 makes it well suited to support a wide variety of industrial, medical, and advanced display applications.

In addition to the DLP9500 DMD, the 0.95 1080p chipset includes a dedicated DLPC410 controller required for high speed pattern rates of 23,148 Hz (1-bit binary) and 2,893 Hz (8-bit gray), one unit DLPR410 (DLP Discovery 4100 Configuration PROM), and two units DLPA200 (DMD micromirror drivers).

Reliable function and operation of the DLP9500 requires that it be used in conjunction with the other components of the chipset. A dedicated chipset provides developers easier access to the DMD as well as high speed, independent micromirror control.

DLP9500 is a digitally controlled micro-electromechanical system (MEMS) spatial light modulator (SLM). When coupled to an appropriate optical system, the DLP9500 can be used to modulate the amplitude, direction, and/or phase of incoming light.

Electrically, the DLP9500 consists of a two-dimensional array of 1-bit CMOS memory cells, organized in a grid of 1920 memory cell columns by 1080 memory cell rows. The CMOS memory array is addressed on a row-by-row basis, over four 16-bit LVDS DDR buses. Addressing is handled by a serial control bus. The specific CMOS memory access protocol is handled by the DLPC410 digital controller.

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Technical documentation

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

DLPLCR95EVM — DLP9500 DMD evaluation board

This DLP evaluation module (EVM) houses DLP9500, a 0.95 1080p 2xLVDS Type-A DMD containing over two million micromirrors with 10.8 µm pitch. When paired with DLPLCRC410EVM, users get pixel accurate control with 1-bit pattern rates up to 23,148 Hz. DLPLCR95EVM is the right evaluation choice (...)
User guide: PDF
Not available on TI.com
Evaluation board

DLPLCRC410EVM — DLPLCRC410 Evaluation Module

The DLPLCRC410EVM, paired with one of five other DMD-based EVMs, is an evaluation platform exhibiting advanced light control for applications like lithography, 3D Printing (SLS and SLA), Machine Vision, and Marking and Coding. This EVM enables evaluations of new customer illumination sources, (...)
User guide: PDF
Not available on TI.com
Optical module

DLP-OMM-SEARCH — DLP® Products third-party search tools

To best meet your design needs and accelerate your time-to-market, DLP® Products works with a variety of third parties to help with everything from optical modules and hardware design to specialty software and other production services. Download one or both search tools listed below to quickly (...)

Simulation model

DLP9500 IBIS Model

DLPC063.ZIP (35 KB) - IBIS Model
3D DMD mechanical geometry

DLP9500/9500UV DMD With FLN Package (Type-A) 3D-CAD Geometry

DLPM065.ZIP (21 KB)
Simulation tool

DLPR410-IBIS — DLPR410 IBIS Model

IBIS file for the DLPR410 PROM device which supports the DLPC410, DLP650LNIR, DLP7000, DLP7000UV, DLP9500 and DLP9500UV.
From: Xilinx
Package Pins Download
CLGA (FLN) 355 View options

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