DLP9500

• 0.95-Inch Diagonal Micromirror Array
  • 1920 × 1080 Array of Aluminum, Micrometer-Sized Mirrors (1080p Resolution)
  • 10.8-µm Micromirror Pitch
  • ±12° Micromirror Tilt Angle (Relative to Flat State)
  • Designed for Corner Illumination
• Designed for Use with Visible Light
  (400 to 700 nm):
  • Window Transmission 96% (Single Pass, Through Two Window Surfaces)
  • Micromirror Reflectivity 89%
  • Array Diffraction Efficiency 87%
  • Array Fill Factor 94%
• Four 16-Bit, Low-Voltage Differential Signaling (LVDS), Double Data Rate (DDR) Input Data Buses
• Up to 400-MHz Input Data Clock Rate
• 42.2-mm × 42.2-mm × 7-mm Package Footprint
• Hermetic Package

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The DLP9500 1080p chipset is part of the DLP^® Discovery™ 4100 platform, which enables high resolution and high performance spatial light modulation. The DLP9500 is the digital micromirror device (DMD) fundamental to the 0.95 1080p chipset. The DLP Discovery 4100 platform also provides the highest level of individual micromirror control with the option for random row addressing. Combined with a hermetic package, the unique capability and value offered by DLP9500 makes it well suited to support a wide variety of industrial, medical, and advanced display applications.

In addition to the DLP9500 DMD, the 0.95 1080p chipset includes a dedicated DLPC410 controller required for high speed pattern rates of 23,148 Hz (1-bit binary) and 2,893 Hz (8-bit gray), one unit DLPR410 (DLP Discovery 4100 Configuration PROM), and two units DLPA200 (DMD micromirror drivers).

Reliable function and operation of the DLP9500 requires that it be used in conjunction with the other components of the chipset. A dedicated chipset provides developers easier access to the DMD as well as high speed, independent micromirror control.

DLP9500 is a digitally controlled micro-electromechanical system (MEMS) spatial light modulator (SLM). When coupled to an appropriate optical system, the DLP9500 can be used to modulate the amplitude, direction, and/or phase of incoming light.

Electrically, the DLP9500 consists of a two-dimensional array of 1-bit CMOS memory cells, organized in a grid of 1920 memory cell columns by 1080 memory cell rows. The CMOS memory array is addressed on a row-by-row basis, over four 16-bit LVDS DDR buses. Addressing is handled by a serial control bus. The specific CMOS memory access protocol is handled by the DLPC410 digital controller.