SPRSPA1 Data sheet

SPRSPA1B March 2025 – November 2025 AM62L

PRODUCTION DATA

1
1 Features
2 Applications
3 Description
1. 3.1 Functional Block Diagram
4 Device Comparison
1. 4.1 Related Products
5 Terminal Configuration and Functions
1. 5.1 Pin Diagrams
2. 5.2 Pin Attributes
  1. 11
  2. 12
3. 5.3 Signal Descriptions
  1. 14
  2. 5.3.1 ADC
    1. 5.3.1.1 MAIN Domain
      1. 17
  3. 5.3.2 CPSW3G
    1. 5.3.2.1 MAIN Domain
      1. 20
      2. 21
      3. 22
      4. 23
  4. 5.3.3 CPTS
    1. 5.3.3.1 MAIN Domain
      1. 26
  5. 5.3.4 DDRSS
    1. 5.3.4.1 MAIN Domain
      1. 29
  6. 5.3.5 DSI
    1. 5.3.5.1 MAIN Domain
      1. 32
  7. 5.3.6 DSS
    1. 5.3.6.1 MAIN Domain
      1. 35
  8. 5.3.7 ECAP
    1. 5.3.7.1 MAIN Domain
      1. 38
      2. 39
      3. 40
  9. 5.3.8 Emulation and Debug
    1. 5.3.8.1 MAIN Domain
      1. 43
    2. 5.3.8.2 WKUP Domain
      1. 45
  10. 5.3.9 EPWM
    1. 5.3.9.1 MAIN Domain
      1. 48
      2. 49
      3. 50
      4. 51
  11. 5.3.10 EQEP
    1. 5.3.10.1 MAIN Domain
      1. 54
      2. 55
      3. 56
  12. 5.3.11 GPIO
    1. 5.3.11.1 MAIN Domain
      1. 59
    2. 5.3.11.2 WKUP Domain
      1. 61
  13. 5.3.12 GPMC
    1. 5.3.12.1 MAIN Domain
      1. 64
  14. 5.3.13 I2C
    1. 5.3.13.1 MAIN Domain
      1. 67
      2. 68
      3. 69
      4. 70
    2. 5.3.13.2 WKUP Domain
      1. 72
  15. 5.3.14 MCAN
    1. 5.3.14.1 MAIN Domain
      1. 75
      2. 76
      3. 77
  16. 5.3.15 MCASP
    1. 5.3.15.1 MAIN Domain
      1. 80
      2. 81
      3. 82
  17. 5.3.16 MCSPI
    1. 5.3.16.1 MAIN Domain
      1. 85
      2. 86
      3. 87
      4. 88
  18. 5.3.17 MDIO
    1. 5.3.17.1 MAIN Domain
      1. 91
  19. 5.3.18 MMC
    1. 5.3.18.1 MAIN Domain
      1. 94
      2. 95
      3. 96
  20. 5.3.19 OSPI
    1. 5.3.19.1 MAIN Domain
      1. 99
  21. 5.3.20 Power Supply
    1. 101
  22. 5.3.21 Reserved
    1. 103
  23. 5.3.22 System and Miscellaneous
    1. 5.3.22.1 Boot Mode Configuration
      1. 5.3.22.1.1 MAIN Domain
        
        107
    2. 5.3.22.2 Clock
      1. 5.3.22.2.1 RTC Domain
        
        110
      2. 5.3.22.2.2 WKUP Domain
        
        112
    3. 5.3.22.3 System
      1. 5.3.22.3.1 MAIN Domain
        
        115
      2. 5.3.22.3.2 RTC Domain
        
        117
      3. 5.3.22.3.3 WKUP Domain
        
        119
  24. 5.3.23 TIMER
    1. 5.3.23.1 MAIN Domain
      1. 122
    2. 5.3.23.2 WKUP Domain
      1. 124
  25. 5.3.24 UART
    1. 5.3.24.1 MAIN Domain
      1. 127
      2. 128
      3. 129
      4. 130
      5. 131
      6. 132
      7. 133
    2. 5.3.24.2 WKUP Domain
      1. 135
  26. 5.3.25 USB
    1. 5.3.25.1 MAIN Domain
      1. 138
      2. 139
4. 5.4 Pin Connectivity Requirements
6 Specifications
7 Detailed Description
8 Applications, Implementation, and Layout
9 Device and Documentation Support
Revision History
10Mechanical, Packaging, and Orderable Information
1. 10.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

ANB|373

Thermal pad, mechanical data (Package|Pins)

Orderable Information

sprspa1b_oa

6.11.3.2 Clock Timing

Tables and figures provided in this section define timing conditions, timing requirements, and switching characteristics for clock signals.

Table 6-15 Clock Timing Conditions

PARAMETER			MIN	MAX	UNIT
INPUT CONDITIONS
SR_I	Input slew rate		0.5		V/ns
OUTPUT CONDITIONS
C_L	Output load capacitance	5ns ≤ t_c < 8ns		5	pF
		8ns ≤ t_c < 20ns		10	pF
		20ns ≤ t_c		30	pF

Table 6-16 Clock Timing Requirements see Figure 6-18

NO.			MIN	MAX	UNIT
CLK1	t_{c(EXT_REFCLK1)}	Cycle time minimum, EXT_REFCLK1	10		ns
CLK2	t_{w(EXT_REFCLK1H)}	Pulse Duration, EXT_REFCLK1 high	E*0.45⁽¹⁾	E*0.55⁽¹⁾	ns
CLK3	t_{w(EXT_REFCLK1L)}	Pulse Duration, EXT_REFCLK1 low	E*0.45⁽¹⁾	E*0.55⁽¹⁾	ns
CLK1	t_{c(WKUP_EXT_REFCLK0)}	Cycle time minimum, WKUP_EXT_REFCLK0	10		ns
CLK2	t_{w(WKUP_EXT_REFCLK0H)}	Pulse Duration, WKUP_EXT_REFCLK0 high	F*0.45⁽²⁾	F*0.55⁽²⁾	ns
CLK3	t_{w(WKUP_EXT_REFCLK0L)}	Pulse Duration, WKUP_EXT_REFCLK0 low	F*0.45⁽²⁾	F*0.55⁽²⁾	ns
CLK1	t_{c(AUDIO_EXT_REFCLK0)}	Cycle time minimum, AUDIO_EXT_REFCLK0	20		ns
CLK2	t_{w(AUDIO_EXT_REFCLK0H)}	Pulse Duration, AUDIO_EXT_REFCLK0 high	G*0.45⁽³⁾	G*0.55⁽³⁾	ns
CLK3	t_{w(AUDIO_EXT_REFCLK0L)}	Pulse Duration, AUDIO_EXT_REFCLK0 low	G*0.45⁽³⁾	G*0.55⁽³⁾	ns
CLK1	t_{c(AUDIO_EXT_REFCLK1)}	Cycle time minimum, AUDIO_EXT_REFCLK1	20		ns
CLK2	t_{w(AUDIO_EXT_REFCLK1H)}	Pulse Duration, AUDIO_EXT_REFCLK1 high	H*0.45⁽⁴⁾	H*0.55⁽⁴⁾	ns
CLK3	t_{w(AUDIO_EXT_REFCLK1L)}	Pulse Duration, AUDIO_EXT_REFCLK1 low	H*0.45⁽⁴⁾	H*0.55⁽⁴⁾	ns

(1) E = EXT_REFCLK1 cycle time in ns.

(2) F = WKUP_EXT_REFCLK0 cycle time in ns.

(3) G = AUDIO_EXT_REFCLK0 cycle time in ns.

(4) H = AUDIO_EXT_REFCLK1 cycle time in ns.

Figure 6-18 Clock Timing Requirements

Table 6-17 Clock Switching Characteristics see Figure 6-19

NO.	PARAMETER		MIN	MAX	UNIT
CLK4	t_c(OBSCLK0)	Cycle time minimum, OBSCLK0	5		ns
CLK5	t_w(OBSCLK0H)	Pulse Duration, OBSCLK0 high	B*0.45⁽¹⁾	B*0.55⁽¹⁾	ns
CLK6	t_w(OBSCLK0L)	Pulse Duration, OBSCLK0 low	B*0.45⁽¹⁾	B*0.55⁽¹⁾	ns
CLK4	t_c(OBSCLK1)	Cycle time minimum, OBSCLK1	5		ns
CLK5	t_w(OBSCLK1H)	Pulse Duration, OBSCLK1 high	F*0.45⁽²⁾	F*0.55⁽²⁾	ns
CLK6	t_w(OBSCLK1L)	Pulse Duration, OBSCLK1 low	F*0.45⁽²⁾	F*0.55⁽²⁾	ns
CLK4	t_c(CLKOUT0)	Cycle time minimum, CLKOUT0	20		ns
CLK5	t_w(CLKOUT0H)	Pulse Duration, CLKOUT0 high	C*0.4⁽³⁾	C*0.6⁽³⁾	ns
CLK6	t_w(CLKOUT0L)	Pulse Duration, CLKOUT0 low	C*0.4⁽³⁾	C*0.6⁽³⁾	ns
CLK4	t_{c(WKUP_SYSCLKOUT0)}	Cycle time minimum, WKUP_SYSCLKOUT0	10		ns
CLK5	t_{w(WKUP_SYSCLKOUT0H)}	Pulse Duration, WKUP_SYSCLKOUT0 high	E*0.4⁽⁴⁾	E*0.6⁽⁴⁾	ns
CLK6	t_{w(WKUP_SYSCLKOUT0L)}	Pulse Duration, WKUP_SYSCLKOUT0 low	E*0.4⁽⁴⁾	E*0.6⁽⁴⁾	ns
CLK4	t_{c(WKUP_OBSCLK0)}	Cycle time minimum, WKUP_OBSCLK0	5		ns
CLK5	t_{w(WKUP_OBSCLK0H)}	Pulse Duration, WKUP_OBSCLK0 high	D*0.45⁽⁵⁾	D*0.55⁽⁵⁾	ns
CLK6	t_{w(WKUP_OBSCLK0L)}	Pulse Duration, WKUP_OBSCLK0 low	D*0.45⁽⁵⁾	D*0.55⁽⁵⁾	ns
CLK4	t_{c(WKUP_CLKOUT0)}	Cycle time minimum, WKUP_CLKOUT0	5		ns
CLK5	t_{w(WKUP_CLKOUT0H)}	Pulse Duration, WKUP_CLKOUT0 high	W*0.4⁽⁶⁾	W*0.6⁽⁶⁾	ns
CLK6	t_{w(WKUP_CLKOUT0L)}	Pulse Duration, WKUP_CLKOUT0 low	W*0.4⁽⁶⁾	W*0.6⁽⁶⁾	ns
CLK4	t_{c(AUDIO_EXT_REFCLK0 )}	Cycle time minimum, AUDIO_EXT_REFCLK0 (McASP Clock Source)	20		ns
CLK4	t_{c(AUDIO_EXT_REFCLK0 )}	Cycle time minimum, AUDIO_EXT_REFCLK0 (PLL Clock Source)	10		ns
CLK5	t_{w(AUDIO_EXT_REFCLK0 H)}	Pulse Duration, AUDIO_EXT_REFCLK0 high	G*0.4⁽⁷⁾	G*0.6⁽⁷⁾	ns
CLK6	t_{w(AUDIO_EXT_REFCLK0 L)}	Pulse Duration, AUDIO_EXT_REFCLK0 low	G*0.4⁽⁷⁾	G*0.6⁽⁷⁾	ns
CLK4	t_{c(AUDIO_EXT_REFCLK1 )}	Cycle time minimum, AUDIO_EXT_REFCLK1 (McASP Clock Source)	20		ns
CLK4	t_{c(AUDIO_EXT_REFCLK1 )}	Cycle time minimum, AUDIO_EXT_REFCLK1 (PLL Clock Source)	10		ns
CLK5	t_{w(AUDIO_EXT_REFCLK1 H)}	Pulse Duration, AUDIO_EXT_REFCLK1 high	J*0.4⁽⁸⁾	J*0.6⁽⁸⁾	ns
CLK6	t_{w(AUDIO_EXT_REFCLK1 L)}	Pulse Duration, AUDIO_EXT_REFCLK1 low	J*0.4⁽⁸⁾	J*0.6⁽⁸⁾	ns

(1) B = OBSCLK0 cycle time in ns.

(2) F = OBSCLK1 cycle time in ns.

(3) C = CLKOUT0 cycle time in ns.

(4) E = WKUP_SYSCLKOUT0 cycle time in ns.

(5) D = WKUP_OBSCLK0 cycle time in ns.

(6) W = WKUP_CLKOUT0 cycle time in ns.

(7) G = AUDIO_EXT_REFCLK0 cycle time in ns.

(8) J = AUDIO_EXT_REFCLK1 cycle time in ns.

Figure 6-19 Clock Switching Characteristics