SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.20.2.4 CONTROLSS_PWMXBAR_FLAG_CLR Register

20.2.4.1 CONTROLSS_PWMXBAR_FLAG_CLR Register (Offset = 1Ch) [reset = 0h]

Output Signal Latched Flag Clear.

Table 3-2747 Instance Table

Instance Name	Physical Address
CONTROLSS_PWMXBAR	502D 101Ch

Figure 3-1336 CONTROLSS_PWMXBAR_FLAG_CLR Name Register

31	30	29	28	27	26	25	24
RESERVED		PWMXBAR_FLAG_CLR_BIT29	PWMXBAR_FLAG_CLR_BIT28	PWMXBAR_FLAG_CLR_BIT27	PWMXBAR_FLAG_CLR_BIT26	PWMXBAR_FLAG_CLR_BIT25	PWMXBAR_FLAG_CLR_BIT24
NONE		R/W	R/W	R/W	R/W	R/W	R/W
0h		0h	0h	0h	0h	0h	0h
23	22	21	20	19	18	17	16
PWMXBAR_FLAG_CLR_BIT23	PWMXBAR_FLAG_CLR_BIT22	PWMXBAR_FLAG_CLR_BIT21	PWMXBAR_FLAG_CLR_BIT20	PWMXBAR_FLAG_CLR_BIT19	PWMXBAR_FLAG_CLR_BIT18	PWMXBAR_FLAG_CLR_BIT17	PWMXBAR_FLAG_CLR_BIT16
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h
15	14	13	12	11	10	9	8
PWMXBAR_FLAG_CLR_BIT15	PWMXBAR_FLAG_CLR_BIT14	PWMXBAR_FLAG_CLR_BIT13	PWMXBAR_FLAG_CLR_BIT12	PWMXBAR_FLAG_CLR_BIT11	PWMXBAR_FLAG_CLR_BIT10	PWMXBAR_FLAG_CLR_BIT9	PWMXBAR_FLAG_CLR_BIT8
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h
7	6	5	4	3	2	1	0
PWMXBAR_FLAG_CLR_BIT7	PWMXBAR_FLAG_CLR_BIT6	PWMXBAR_FLAG_CLR_BIT5	PWMXBAR_FLAG_CLR_BIT4	PWMXBAR_FLAG_CLR_BIT3	PWMXBAR_FLAG_CLR_BIT2	PWMXBAR_FLAG_CLR_BIT1	PWMXBAR_FLAG_CLR_BIT0
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h

Table 3-2748 CONTROLSS_PWMXBAR_FLAG_CLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31:30	RESERVED	NONE	0h	Reserved
29	PWMXBAR_FLAG_CLR_BIT29	R/W	0h	Output Signal Latched Flag Clear
28	PWMXBAR_FLAG_CLR_BIT28	R/W	0h	Output Signal Latched Flag Clear
27	PWMXBAR_FLAG_CLR_BIT27	R/W	0h	Output Signal Latched Flag Clear
26	PWMXBAR_FLAG_CLR_BIT26	R/W	0h	Output Signal Latched Flag Clear
25	PWMXBAR_FLAG_CLR_BIT25	R/W	0h	Output Signal Latched Flag Clear
24	PWMXBAR_FLAG_CLR_BIT24	R/W	0h	Output Signal Latched Flag Clear
23	PWMXBAR_FLAG_CLR_BIT23	R/W	0h	Output Signal Latched Flag Clear
22	PWMXBAR_FLAG_CLR_BIT22	R/W	0h	Output Signal Latched Flag Clear
21	PWMXBAR_FLAG_CLR_BIT21	R/W	0h	Output Signal Latched Flag Clear
20	PWMXBAR_FLAG_CLR_BIT20	R/W	0h	Output Signal Latched Flag Clear
19	PWMXBAR_FLAG_CLR_BIT19	R/W	0h	Output Signal Latched Flag Clear
18	PWMXBAR_FLAG_CLR_BIT18	R/W	0h	Output Signal Latched Flag Clear
17	PWMXBAR_FLAG_CLR_BIT17	R/W	0h	Output Signal Latched Flag Clear
16	PWMXBAR_FLAG_CLR_BIT16	R/W	0h	Output Signal Latched Flag Clear
15	PWMXBAR_FLAG_CLR_BIT15	R/W	0h	Output Signal Latched Flag Clear
14	PWMXBAR_FLAG_CLR_BIT14	R/W	0h	Output Signal Latched Flag Clear
13	PWMXBAR_FLAG_CLR_BIT13	R/W	0h	Output Signal Latched Flag Clear
12	PWMXBAR_FLAG_CLR_BIT12	R/W	0h	Output Signal Latched Flag Clear
11	PWMXBAR_FLAG_CLR_BIT11	R/W	0h	Output Signal Latched Flag Clear
10	PWMXBAR_FLAG_CLR_BIT10	R/W	0h	Output Signal Latched Flag Clear
9	PWMXBAR_FLAG_CLR_BIT9	R/W	0h	Output Signal Latched Flag Clear
8	PWMXBAR_FLAG_CLR_BIT8	R/W	0h	Output Signal Latched Flag Clear
7	PWMXBAR_FLAG_CLR_BIT7	R/W	0h	Output Signal Latched Flag Clear
6	PWMXBAR_FLAG_CLR_BIT6	R/W	0h	Output Signal Latched Flag Clear
5	PWMXBAR_FLAG_CLR_BIT5	R/W	0h	Output Signal Latched Flag Clear
4	PWMXBAR_FLAG_CLR_BIT4	R/W	0h	Output Signal Latched Flag Clear
3	PWMXBAR_FLAG_CLR_BIT3	R/W	0h	Output Signal Latched Flag Clear
2	PWMXBAR_FLAG_CLR_BIT2	R/W	0h	Output Signal Latched Flag Clear
1	PWMXBAR_FLAG_CLR_BIT1	R/W	0h	Output Signal Latched Flag Clear
0	PWMXBAR_FLAG_CLR_BIT0	R/W	0h	Output Signal Latched Flag Clear