SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.2.2.150 MSS_CTRL_MSS_PERIPH_ERRAGG_MASK0 Register

2.2.150.1 MSS_CTRL_MSS_PERIPH_ERRAGG_MASK0 Register (Offset = 18010h) [reset = 0h]

This register Masks selected interrupt soures from generating the Aggregated MMR Access Error Interrupt.

Table 2-301 Instance Table

Instance Name	Physical Address
MSS_CTRL	50D1 8010h

Figure 2-150 MSS_CTRL_MSS_PERIPH_ERRAGG_MASK0 Name Register

31	30	29	28	27	26	25	24
RESERVED
NONE
0h
23	22	21	20	19	18	17	16
RESERVED
NONE
0h
15	14	13	12	11	10	9	8
RESERVED				MSS_PERIPH_ERRAGG_MASK0_HSM_CTRL_WR	MSS_PERIPH_ERRAGG_MASK0_HSM_CTRL_RD	MSS_PERIPH_ERRAGG_MASK0_HSM_SOC_CTRL_WR	MSS_PERIPH_ERRAGG_MASK0_HSM_SOC_CTRL_RD
NONE				R/W	R/W	R/W	R/W
0h				0h	0h	0h	0h
7	6	5	4	3	2	1	0
MSS_PERIPH_ERRAGG_MASK0_TOP_RCM_WR	MSS_PERIPH_ERRAGG_MASK0_TOP_RCM_RD	MSS_PERIPH_ERRAGG_MASK0_TOP_CTRL_WR	MSS_PERIPH_ERRAGG_MASK0_TOP_CTRL_RD	MSS_PERIPH_ERRAGG_MASK0_MSS_RCM_WR	MSS_PERIPH_ERRAGG_MASK0_MSS_RCM_RD	MSS_PERIPH_ERRAGG_MASK0_MSS_CTRL_WR	MSS_PERIPH_ERRAGG_MASK0_MSS_CTRL_RD
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h

Table 2-302 MSS_CTRL_MSS_PERIPH_ERRAGG_MASK0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31:12	RESERVED	NONE	0h	Reserved
11	MSS_PERIPH_ERRAGG_MASK0_HSM_CTRL_WR	R/W	0h	Mask Interrupt from HSM_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked
10	MSS_PERIPH_ERRAGG_MASK0_HSM_CTRL_RD	R/W	0h	Mask Interrupt from HSM_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked
9	MSS_PERIPH_ERRAGG_MASK0_HSM_SOC_CTRL_WR	R/W	0h	Mask Interrupt from HSM_SOC_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked
8	MSS_PERIPH_ERRAGG_MASK0_HSM_SOC_CTRL_RD	R/W	0h	Mask Interrupt from HSM_SOC_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked
7	MSS_PERIPH_ERRAGG_MASK0_TOP_RCM_WR	R/W	0h	Mask Interrupt from TOP_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked
6	MSS_PERIPH_ERRAGG_MASK0_TOP_RCM_RD	R/W	0h	Mask Interrupt from TOP_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked
5	MSS_PERIPH_ERRAGG_MASK0_TOP_CTRL_WR	R/W	0h	Mask Interrupt from TOP_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked
4	MSS_PERIPH_ERRAGG_MASK0_TOP_CTRL_RD	R/W	0h	Mask Interrupt from TOP_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked
3	MSS_PERIPH_ERRAGG_MASK0_MSS_RCM_WR	R/W	0h	Mask Interrupt from MSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked
2	MSS_PERIPH_ERRAGG_MASK0_MSS_RCM_RD	R/W	0h	Mask Interrupt from MSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked
1	MSS_PERIPH_ERRAGG_MASK0_MSS_CTRL_WR	R/W	0h	Mask Interrupt from MSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked
0	MSS_PERIPH_ERRAGG_MASK0_MSS_CTRL_RD	R/W	0h	Mask Interrupt from MSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked