SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.2.2.121 ADC_CFG_REP1CTL Register

2.2.121.1 ADC_CFG_REP1CTL Register (Offset = 100h) [reset = 0h]

ADC Trigger Repeater 1 Control Register.

Table 3-245 Instance Table

Instance Name	Physical Address
ADC0_G0_G5	502C 0100h
ADC1_G0_G5	502C 1100h
ADC2_G0_G5	502C 2100h
ADC3_G0_G5	502C 3100h
ADC4_G0_G5	502C 4100h

Figure 3-121 ADC_CFG_REP1CTL Name Register

31	30	29	28	27	26	25	24
RESERVED_5
R
0h
23	22	21	20	19	18	17	16
SWSYNC	RESERVED_4	SYNCINSEL
R/W1TS	R	R/W
0h	0h	0h
15	14	13	12	11	10	9	8
RESERVED_3	TRIGGER
R	R/W
0h	0h
7	6	5	4	3	2	1	0
TRIGGEROVF	PHASEOVF	RESERVED_2	SOCBUSY	MODULEBUSY	RESERVED_1	ACTIVEMODE	MODE
R/W1TC	R/W1TC	R	R	R	R	R	R/W
0h	0h	0h	0h	0h	0h	0h	0h

Table 3-246 ADC_CFG_REP1CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31:24	RESERVED_5	R	0h	Reserved
23	SWSYNC	R/W1TS	0h	Trigger repeater 1 software force sync. On a sync. event, all registers in repeater 1 are reset to a ready and waiting state. Values of NSEL, PHASE, and MODE are preserved. Note: SOCs associated with repeater 1 are not cleared.
22	RESERVED_4	R	0h	Reserved
21:16	SYNCINSEL	R/W	0h	Trigger repeater 1 sync. input select. On a sync. event, all registers in repeater 1 are reset to a ready and waiting state. Values of NSEL, PHASE, and MODE are preserved. Note: SOCs associated with repeater 1 are not cleared.
15	RESERVED_3	R	0h	Reserved
14:8	TRIGGER	R/W	0h	ADC Trigger Repeater 1 Trigger Select. Selects the trigger to modify via oversampling or undersampling. 00h REPTRIG0 - Software only 01h REPTRIG1 - RTI0 Timer 02h REPTRIG2 - RTI1 Timer 03h REPTRIG3 - RTI2 Timer 04h REPTRIG4 - RTI3 Timer 05h REPTRIG5 - InputXBAR.Out[5] 06h REPTRIG6 - spare 07h REPTRIG7 - spare 08h REPTRIG8 - EPWM0, ADCSOCA 09h REPTRIG9 - EPWM0, ADCSOCB 0Ah REPTRIG10 - EPWM1, ADCSOCA 0Bh REPTRIG11 - EPWM1, ADCSOCB 0Ch REPTRIG12 - EPWM2, ADCSOCA 0Dh REPTRIG13 - EPWM2, ADCSOCB 0Eh REPTRIG14 - EPWM3, ADCSOCA 0Fh REPTRIG15 - EPWM3, ADCSOCB .... EPWM4 to EPWM27 40h REPTRIG64 - EPWM28, ADCSOCA 41h REPTRIG65 - EPWM28, ADCSOCB 42h REPTRIG66 - EPWM29, ADCSOCA 43h REPTRIG67 - EPWM29, ADCSOCB 44h REPTRIG68 - EPWM30, ADCSOCA 45h REPTRIG69 - EPWM30, ADCSOCB 46h REPTRIG70 - EPWM31, ADCSOCA 47h REPTRIG71 - EPWM31, ADCSOCB 48h REPTRIG72 - ECAP0, TRIGOUT .... ECAP1 to ECAP8 51h REPTRIG81 - ECAP9, TRIGOUT 52h REPTRIG82 - ECAP10, TRIGOUT .... 57h REPTRIG73 - ECAP15, TRIGOUT 58h REPTRIG1 - RTI4 Timer 59h REPTRIG1 - RTI5 Timer 5Ah REPTRIG1 - RTI6 Timer 5Bh REPTRIG1 - RTI7 Timer .... 7Fh - Reserved
7	TRIGGEROVF	R/W1TC	0h	ADC Trigger Repeater 1 Oversampled Trigger Overflow. Indicates that a trigger was dropped because a trigger arrived while the repeater was still generating repeated oversampled triggers [NCOUNT was not 0 or SOCs associated with Repeater 1 were still pending]. Writing a 1 will clear this flag. Note: This flag won't be set in undersampling mode or when NSEL = 0; if a trigger arrives before the previous SOCs have completed, the trigger will be passed and the overflow flags of the SOCs that were still pending will be set. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set
6	PHASEOVF	R/W1TC	0h	ADC Trigger Repeater 1 Phase Delay Overflow. Indicates that a trigger was dropped because a trigger arrived when the phase delay logic was still waiting to send the delayed trigger [PHASECOUNT was not 0]. Writing a 1 will clear this flag. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set
5	RESERVED_2	R	0h	Reserved
4	SOCBUSY	R	0h	ADC Trigger Repeater 1 Associated SOCs Busy indicator. In oversampling mode: 0 = no SOCs associated with this repeater are pending 1 = SOCs associated with this repeater are still pending The next repeated trigger to the ADC in oversampling mode will not occur until SPREADCOUNT is 0 [minimum time is complete] and REP1CTL.BUSY = 0 [SOCs associated with trigger repeater 1 are no longer pending]. Note: If the ADC is in burstmode and the BURSTTRIG is Repeater 1, then all round-robin SOCs are considered associated with this repeater and the repeater will not re-trigger until there are no pending round-robin SOCs [in addition to any associated pending high-priority SOCs].
3	MODULEBUSY	R	0h	ADC Trigger Repeater 1 Module Busy indicator. In oversampling mode: 0 = Repeater 1 is idle and can accept a new repeated trigger in oversampling mode 1 = Repeater 1 still has repeated triggers remaining [NCOUNT ' 0] or associated SOCs are still pending [SOCBUSY is 1] If a new oversampled trigger is received while the module is still busy, the TRIGGEROVF bit will be set and the trigger will be ignored.
2	RESERVED_1	R	0h	Reserved
1	ACTIVEMODE	R	0h	When a trigger is recived in oversampling or undersampling mode the value of MODE is copied to ACTIVEMODE. ACTIVEMODE determines if the repeater will repeat of filter triggers. Changes to MODE while the repeater is working therefore won't cause any changes in functionality until the module becomes idle and then a new trigger is received. 0 = module is oversampling 1 = module is undersampling
0	MODE	R/W	0h	ADC trigger repeater 1 mode selection. Select either oversampling or undersampling mode. In oversampling mode, when the trigger selected by REP1CTL.TRIGSEL is received, the repeater will repeat the trigger REP1N.NSEL + 1 times. In undersampling mode, when the trigger selected by REP1CTL.TRIGSEL is received the first time, the repeater will pass the trigger through. The next REP1N.NSEL triggers will be ignored. 0 = oversampling 1 = undersampling