SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
ADC Interrupt Flag Clear Register.
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| Instance Name | Physical Address |
|---|---|
| ADC0_G0_G5 | 502C 0008h |
| ADC1_G0_G5 | 502C 1008h |
| ADC2_G0_G5 | 502C 2008h |
| ADC3_G0_G5 | 502C 3008h |
| ADC4_G0_G5 | 502C 4008h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_1 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED_1 | ADCINT4 | ADCINT3 | ADCINT2 | ADCINT1 | |||
| R | R/W1TS | R/W1TS | R/W1TS | R/W1TS | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:4 | RESERVED_1 | R | 0h | Reserved |
| 3 | ADCINT4 | R/W1TS | 0h | ADC Interrupt 4 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set |
| 2 | ADCINT3 | R/W1TS | 0h | ADC Interrupt 3 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set |
| 1 | ADCINT2 | R/W1TS | 0h | ADC Interrupt 2 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set |
| 0 | ADCINT1 | R/W1TS | 0h | ADC Interrupt 1 Flag Clear. Reads return 0. 0 No action 1 Clears respective flag bit in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set |