SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Event Trigger Pre-Scale Register.
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| Instance Name | Physical Address |
|---|---|
| EPWM0_G0 | 5000 014Ch |
| EPWM0_G1 | 5004 014Ch |
| EPWM0_G2 | 5008 014Ch |
| EPWM0_G3 | 500C 014Ch |
| EPWM1_G0 | 5000 114Ch |
| EPWM1_G1 | 5004 114Ch |
| EPWM1_G2 | 5008 114Ch |
| EPWM1_G3 | 500C 114Ch |
| EPWM2_G0 | 5000 214Ch |
| EPWM2_G1 | 5004 214Ch |
| EPWM2_G2 | 5008 214Ch |
| EPWM2_G3 | 500C 214Ch |
| EPWM3_G0 | 5000 314Ch |
| EPWM3_G1 | 5004 314Ch |
| EPWM3_G2 | 5008 314Ch |
| EPWM3_G3 | 500C 314Ch |
| EPWM4_G0 | 5000 414Ch |
| EPWM4_G1 | 5004 414Ch |
| EPWM4_G2 | 5008 414Ch |
| EPWM4_G3 | 500C 414Ch |
| EPWM5_G0 | 5000 514Ch |
| EPWM5_G1 | 5004 514Ch |
| EPWM5_G2 | 5008 514Ch |
| EPWM5_G3 | 500C 514Ch |
| EPWM6_G0 | 5000 614Ch |
| EPWM6_G1 | 5004 614Ch |
| EPWM6_G2 | 5008 614Ch |
| EPWM6_G3 | 500C 614Ch |
| EPWM7_G0 | 5000 714Ch |
| EPWM7_G1 | 5004 714Ch |
| EPWM7_G2 | 5008 714Ch |
| EPWM7_G3 | 500C 714Ch |
| EPWM8_G0 | 5000 814Ch |
| EPWM8_G1 | 5004 814Ch |
| EPWM8_G2 | 5008 814Ch |
| EPWM8_G3 | 500C 814Ch |
| EPWM9_G0 | 5000 914Ch |
| EPWM9_G1 | 5004 914Ch |
| EPWM9_G2 | 5008 914Ch |
| EPWM9_G3 | 500C 914Ch |
| EPWM10_G0 | 5000 A14Ch |
| EPWM10_G1 | 5004 A14Ch |
| EPWM10_G2 | 5008 A14Ch |
| EPWM10_G3 | 500C A14Ch |
| EPWM11_G0 | 5000 B14Ch |
| EPWM11_G1 | 5004 B14Ch |
| EPWM11_G2 | 5008 B14Ch |
| EPWM11_G3 | 500C B14Ch |
| EPWM12_G0 | 5000 C14Ch |
| EPWM12_G1 | 5004 C14Ch |
| EPWM12_G2 | 5008 C14Ch |
| EPWM12_G3 | 500C C14Ch |
| EPWM13_G0 | 5000 D14Ch |
| EPWM13_G1 | 5004 D14Ch |
| EPWM13_G2 | 5008 D14Ch |
| EPWM13_G3 | 500C D14Ch |
| EPWM14_G0 | 5000 E14Ch |
| EPWM14_G1 | 5004 E14Ch |
| EPWM14_G2 | 5008 E14Ch |
| EPWM14_G3 | 500C E14Ch |
| EPWM15_G0 | 5000 F14Ch |
| EPWM15_G1 | 5004 F14Ch |
| EPWM15_G2 | 5008 F14Ch |
| EPWM15_G3 | 500C F14Ch |
| EPWM16_G0 | 5001 014Ch |
| EPWM16_G1 | 5005 014Ch |
| EPWM16_G2 | 5009 014Ch |
| EPWM16_G3 | 500D 014Ch |
| EPWM17_G0 | 5001 114Ch |
| EPWM17_G1 | 5005 114Ch |
| EPWM17_G2 | 5009 114Ch |
| EPWM17_G3 | 500D 114Ch |
| EPWM18_G0 | 5001 214Ch |
| EPWM18_G1 | 5005 214Ch |
| EPWM18_G2 | 5009 214Ch |
| EPWM18_G3 | 500D 214Ch |
| EPWM19_G0 | 5001 314Ch |
| EPWM19_G1 | 5005 314Ch |
| EPWM19_G2 | 5009 314Ch |
| EPWM19_G3 | 500D 314Ch |
| EPWM20_G0 | 5001 414Ch |
| EPWM20_G1 | 5005 414Ch |
| EPWM20_G2 | 5009 414Ch |
| EPWM20_G3 | 500D 414Ch |
| EPWM21_G0 | 5001 514Ch |
| EPWM21_G1 | 5005 514Ch |
| EPWM21_G2 | 5009 514Ch |
| EPWM21_G3 | 500D 514Ch |
| EPWM22_G0 | 5001 614Ch |
| EPWM22_G1 | 5005 614Ch |
| EPWM22_G2 | 5009 614Ch |
| EPWM22_G3 | 500D 614Ch |
| EPWM23_G0 | 5001 714Ch |
| EPWM23_G1 | 5005 714Ch |
| EPWM23_G2 | 5009 714Ch |
| EPWM23_G3 | 500D 714Ch |
| EPWM24_G0 | 5001 814Ch |
| EPWM24_G1 | 5005 814Ch |
| EPWM24_G2 | 5009 814Ch |
| EPWM24_G3 | 500D 814Ch |
| EPWM25_G0 | 5001 914Ch |
| EPWM25_G1 | 5005 914Ch |
| EPWM25_G2 | 5009 914Ch |
| EPWM25_G3 | 500D 914Ch |
| EPWM26_G0 | 5001 A14Ch |
| EPWM26_G1 | 5005 A14Ch |
| EPWM26_G2 | 5009 A14Ch |
| EPWM26_G3 | 500D A14Ch |
| EPWM27_G0 | 5001 B14Ch |
| EPWM27_G1 | 5005 B14Ch |
| EPWM27_G2 | 5009 B14Ch |
| EPWM27_G3 | 500D B14Ch |
| EPWM28_G0 | 5001 C14Ch |
| EPWM28_G1 | 5005 C14Ch |
| EPWM28_G2 | 5009 C14Ch |
| EPWM28_G3 | 500D C14Ch |
| EPWM29_G0 | 5001 D14Ch |
| EPWM29_G1 | 5005 D14Ch |
| EPWM29_G2 | 5009 D14Ch |
| EPWM29_G3 | 500D D14Ch |
| EPWM30_G0 | 5001 E14Ch |
| EPWM30_G1 | 5005 E14Ch |
| EPWM30_G2 | 5009 E14Ch |
| EPWM30_G3 | 500D E14Ch |
| EPWM31_G0 | 5001 F14Ch |
| EPWM31_G1 | 5005 F14Ch |
| EPWM31_G2 | 5009 F14Ch |
| EPWM31_G3 | 500D F14Ch |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SOCBCNT | SOCBPRD | SOCACNT | SOCAPRD | ||||
| R | R/W | R | R/W | ||||
| 0h | 0h | 0h | 0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED_1 | SOCPSSEL | INTPSSEL | INTCNT | INTPRD | |||
| R | R/W | R/W | R | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:14 | SOCBCNT | R | 0h | EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have occurred. |
| 13:12 | SOCBPRD | R/W | 0h | EPWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated, the pulse must be enabled [ETSEL[SOCBEN] = 1]. The SOCB pulse will be generated even if the status flag is set from a previous start of conversion [ETFLG[SOCB] = 1]. Once the SOCB pulse is generated, the ETPS[SOCBCNT] bits will automatically be cleared. 00:Disable the SOCB event counter. No EPWMxSOCB pulse will be generated 01:Generate the EPWMxSOCB pulse on the first event: ETPS[SOCBCNT] = 2'b01 10:Generate the EPWMxSOCB pulse on the second event: ETPS[SOCBCNT] = 2'b10 11:Generate the EPWMxSOCB pulse on the third event: ETPS[SOCBCNT] = 2'b11 |
| 11:10 | SOCACNT | R | 0h | EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have occurred. |
| 9:8 | SOCAPRD | R/W | 0h | EPWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated, the pulse must be enabled [ETSEL[SOCAEN] = 1]. The SOCA pulse will be generated even if the status flag is set from a previous start of conversion [ETFLG[SOCA] = 1]. Once the SOCA pulse is generated, the ETPS[SOCACNT] bits will automatically be cleared. 00:Disable the SOCA event counter. No EPWMxSOCA pulse will be generated 01:Generate the EPWMxSOCA pulse on the first event: ETPS[SOCACNT] = 2'b01 10:Generate the EPWMxSOCA pulse on the second event: ETPS[SOCACNT] = 2'b10 11:Generate the EPWMxSOCA pulse on the third event: ETPS[SOCACNT] = 2'b11 |
| 7:6 | RESERVED_1 | R | 0h | Reserved |
| 5 | SOCPSSEL | R/W | 0h | EPWMxSOC A/B Pre-Scale Selection Bits 0:Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers to determine frequency of events [interrupt once every 0-15 events]. |
| 4 | INTPSSEL | R/W | 0h | EPWMxINTn Pre-Scale Selection Bits 0:Selects ETPS [INTCNT, and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1:Selects ETINTPS [ INTCNT2, and INTPRD2 ] registers to determine frequency of events [interrupt once every 0-15 events]. |
| 3:2 | INTCNT | R | 0h | EPWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled, ETSEL[INT] = 0 or the interrupt flag is set, ETFLG[INT] = 1, the counter will stop counting events when it reaches the period value ETPS[INTCNT] = ETPS[INTPRD]. 00:No events have occurred. 01:1 event has occurred. 10:2 events have occurred. 11:3 events have occurred. |
| 1:0 | INTPRD | R/W | 0h | EPWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated, the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is set from a previous interrupt [ETFLG[INT] = 1] then no interrupt will be generated until the flag is cleared via the ETCLR[INT] bit. This allows for one interrupt to be pending while another is still being serviced. Once the interrupt is generated, the ETPS[INTCNT] bits will automatically be cleared. Writing a INTPRD value that is the same as the current counter value will trigger an interrupt if it is enabled and the status flag is clear. Writing a INTPRD value that is less than the current counter value will result in an undefined state. If a counter event occurs at the same instant as a new zero or non-zero INTPRD value is written, the counter is incremented. 00:Disable the interrupt event counter. No interrupt will be generated and ETFRC[INT] is ignored. 01:Generate an interrupt on the first event INTCNT = 01 [first event] 10:Generate interrupt on ETPS[INTCNT] = 2'b10 [second event] 11:Generate interrupt on ETPS[INTCNT] = 2'b11 [third event] |