SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

4.2.2.206 ICSSM_PR1_ICSS_UART_UART_SLV_LCR Register

2.2.206.1 ICSSM_PR1_ICSS_UART_UART_SLV_LCR Register (Offset = Ch) [reset = 0h]

Line Control Register (LCR)
The system programmer controls the format of the asynchronous data communication exchange by using LCR. In addition, the programmer can retrieve, inspect, and modify the content of LCR; this eliminates the need for separate storage of the line characteristics in system memory.

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Table 4-833 Instance Table

Instance Name	Physical Address
ICSSM0	4802 800Ch

Figure 4-400 ICSSM_PR1_ICSS_UART_UART_SLV_LCR Name Register

31	30	29	28	27	26	25	24
RESERVED
NONE
0h
23	22	21	20	19	18	17	16
RESERVED
NONE
0h
15	14	13	12	11	10	9	8
RESERVED
NONE
0h
7	6	5	4	3	2	1	0
DLAB	BC	SP	EPS	PEN	STB	WLS1	WLS
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h

Table 4-834 ICSSM_PR1_ICSS_UART_UART_SLV_LCR Register Field Descriptions

Bit	Field	Type	Reset	Description
31:8	RESERVED	NONE	0h	Reserved
7	DLAB	R/W	0h	Divisor latch access bit. The divisor latch registers (DLL and DLH) can be accessed at dedicated addresses or at addresses shared by RBR, THR, and IER. Using the shared addresses requires toggling DLAB to change which registers are selected. If you use the dedicated addresses, you can keep DLAB = 0. 1 Allows access to the divisor latches of the baud generator during a read or write operation (DLL and DLH). At the address shared by RBR, THR, and DLL, the CPU can read from and write to DLL. At the address shared by IER and DLH, the CPU can read from and write to DLH. 0 Allows access to the receiver buffer register (RBR), the transmitter holding register (THR), and the interrupt enable register (IER) selected. At the address shared by RBR, THR, and DLL, the CPU can read from RBR and write to THR. At the address shared by IER and DLH, the CPU can read from and write to IER.
6	BC	R/W	0h	Break Control 1 Break condition is transmitted to the receiving UART. A break condition is a condition where the UARTn_TXD signal is forced to the spacing (cleared) state. 0 Break condition is disabled
5	SP	R/W	0h	Stick parity. The SP bit works in conjunction with the EPS and PEN bits. 1 Stick parity is enabled -When odd parity is selected (EPS = 0), the PARITY bit is transmitted and checked as set. -When even parity is selected (EPS = 1), the PARITY bit is transmitted and checked as cleared. 0 Stick parity is disabled
4	EPS	R/W	0h	Even parity select. Selects the parity when parity is enabled (PEN = 1). The EPS bit works in conjunction with the SP and PEN bits. 1 Even parity is selected (an even number of logic 1s is transmitted or checked in the data and PARITY bits). 0 Odd parity is selected (an odd number of logic 1s is transmitted or checked in the data and PARITY bits).
3	PEN	R/W	0h	Parity enable. The PEN bit works in conjunction with the SP and EPS bits. 1 Parity bit is generated in transmitted data and is checked in received data between the last data word bit and the first STOP bit. 0 No PARITY bit is transmitted or checked.
2	STB	R/W	0h	Number of STOP bits generated. STB specifies 1, 1.5, or 2 STOP bits in each transmitted character. When STB = 1, the WLS bit determines the number of STOP bits. The receiver clocks only the first STOP bit, regardless of the number of STOP bits selected. 1 WLS bit determines the number of STOP bits: -When WLS = 0, 1.5 STOP bits are generated. -When WLS = 1h, 2h, or 3h, 2 STOP bits are generated. 0 1 STOP bit is generated.
1	WLS1	R/W	0h	Word Length Select Bit 1
0	WLS	R/W	0h	Word length select. Number of bits in each transmitted or received serial character. When STB = 1, the WLS bit determines the number of STOP bits. 3 8 bits 2 7 bits 1 6 bits 0 5 bits