SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
The SCIFLR register indicates the current status of the various interrupt sources of the LIN module.
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| Instance Name | Physical Address |
|---|---|
| LIN0 | 5240 001Ch |
| LIN1 | 5240 101Ch |
| LIN2 | 5240 201Ch |
| LIN3 | 5240 301Ch |
| LIN4 | 5240 401Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| BE | PBE | CE | ISFE | NRE | FE | OE | PE |
| R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_3 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_2 | IDRXFLAG | IDTXFLAG | RXWAKE | TXEMPTY | TXWAKE | RXRDY | TXRDY |
| R | R/W1TC | R/W1TC | R | R | R/W | R/W1TC | R |
| 0h | 0h | 0h | 0h | 1h | 0h | 0h | 1h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TOA3WUS | TOAWUS | RESERVED_1 | TIMEOUT | BUSY | IDLE | WAKEUP | BRKDT |
| R/W1TC | R/W1TC | R | R/W1TC | R | R | R/W1TC | R/W1TC |
| 0h | 0h | 0h | 0h | 0h | 1h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | BE | R/W1TC | 0h | Bit Error Flag. This bit is effective in LIN mode only. This bit is set when there has been a bit error. This is detected by the bit monitor in the internal bit monitor. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit [SCIGCR1.7] - RESET bit [SCIGCR0.0] - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only. 1 Bit error detected. 0 No bit error detected. |
| 30 | PBE | R/W1TC | 0h | Physical Bus Error Flag. This bit is effective in LIN mode only. This bit is set when there has been a physical bus error. This is detected by the bit monitor in TED. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit [SCIGCR1.7] - RESET bit [SCIGCR0.0] - System reset - Writing a 1 to this bit - Reception of a new sync break Note: thie PBE will ony be flagged if no sync break can be generated. [because of a bus shortage to VBAT] or if no sync break delimeter can be generated [because of a bus shortage to GND]. This field is writable in LIN mode only. 1 Physical bus error detected. 0 No physiscal bus error detected. |
| 29 | CE | R/W1TC | 0h | Checksum Error Flag. This bit is effective in LIN mode only. This bit is set when there is checksum error detected by a receiving node. The type of checksum to be used depends on the SCIGCR1.CTYPE bit. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit [SCIGCR1.7] - RESET bit [SCIGCR0.0] - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only. 1 Checksum error detected. 0 No Checksum error detected. |
| 28 | ISFE | R/W1TC | 0h | Inconsistent Sync Field Error Flag. This bit is effective in LIN mode only. This bit is set when there has been an inconsistent Sync Field error detected by the synchronizer during header reception. See the "Header Reception and Adaptive Baudrate" section for more information. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit [SCIGCR1.7] - RESET bit [SCIGCR0.0] - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only. 1 Inconsistent Sync Field error detected. 0 No Inconsistent Sync Field error detected. |
| 27 | NRE | R/W1TC | 0h | No-Response Error Flag. This bit is effective in LIN mode only. This bit is set when there is no response to a master's header completed within TFRAME_MAX. This timeout period is applied for message frames of unknown length [identifiers 0 to 61]. This error is detected by the synchronizer of the module. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit [SCIGCR1.7] - RESET bit [SCIGCR0.0] - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only. 1 No-Response error detected. 0 No No-Response error detected. |
| 26 | FE | R/W1TC | 0h | Framing error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when an expected stop bit is not found. In SCI compatible mode, only the first stop bit is checked. The missing stop bit indicates that synchronization with the start bit has been lost and that the character is incorrectly framed. Detection of a framing error causes the SCI to generate an error interrupt if the RXERR INT ENA bit is set. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit [SCIGCR1.7] - RESET bit [SCIGCR0.0] - System reset - Writing a 1 to this bit - Reception of a new character [SCI-compatible mode], or frame [LIN mode] In multibuffer mode the frame is defined in the SCIFORMAT register. 1 Framing error detected. 0 No framing error detected. |
| 25 | OE | R/W1TC | 0h | Overrun error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD or the RDy buffers. Detection of an overrun error causes the LIN to generate an error interrupt if the SET OE INT bit is one. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit [SCIGCR1.7] - RESET bit [SCIGCR0.0] - System reset - Writing a 1 to this bit 1 Overrun error detected. 0 No overrun error detected. |
| 24 | PE | R/W1TC | 0h | Parity error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when a parity error is detected in the received data. In SCI address-bit mode, the parity is calculated on the data and address bit fields of the received frame. In idle-line mode, only the data is used to calculate parity. An error is generated when a character is received with a mismatch between the number of 1s and its parity bit. For more information on parity checking, see the "SCI Global Control Register [SCIGCR1]" description. If the parity function is disabled [that is, SCIGCR1.2 = 0], the PE flag is disabled and read as 0. Detection of a parity error causes the LIN to generate an error interrupt if the SET PE INT bit = 1. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit [SCIGCR1.7] - RESET bit [SCIGCR0.0] - System reset - Reception of a new charcter [SCI-compatible mode] or frame [LIN mode] - Writing a 1 to this bit 1 Parity error detected. 0 No parity error or parity disabled. |
| 23:16 | RESERVED_3 | R | 0h | Reserved |
| 15 | RESERVED_2 | R | 0h | Reserved |
| 14 | IDRXFLAG | R/W1TC | 0h | Identifier On Receive Flag. This bit is effective in LIN mode only. This flag is set once an identifier is received with an RX match and no ID-parity error. See the "Message Filtering and Validation" section for more details. When this flag is set it indicates that a new valid identifier has been received on an RX match. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit [SCIGCR1.7] - RESET bit [SCIGCR0.0] - System reset - Reading the LINID register - Writing a 1 to this bit This field is writable in LIN mode only. 1 Valid ID RX received in LINID[23:16] on RX
match.
0 No valid ID received. |
| 13 | IDTXFLAG | R/W1TC | 0h | Identifier On Transmit Flag. This bit is effective in LIN mode only. This flag is set once an identifier is received with a TX match and no ID-parity error. See the "Message Filtering and Validation" section for more details. When this flag is set it indicates that a new valid identifier has been received on a TX match. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - RESET bit [SCIGCR0.0] - Setting SWnRESET - System reset - Reading the LINID register - Writing a 1 to this bit This field is writable in LIN mode only. 1 Valid ID received in LINID[23:16] on TX
match.
0 No valid ID received. |
| 12 | RXWAKE | R | 0h | Receiver wakeup detect flag. This bit is effective in SCI-compatible mode only. The SCI sets this bit to indicate that the data currently in SCIRD is an address. This bit is cleared by: - RESET bit - Setting the SWnRESET bit [SCIGCR1.7] - System reset - Receipt of a data frame This bit is writable in SCI mode only. 1 The data in SCIRD is an address. |
| 11 | TXEMPTY | R | 1h | Transmitter Empty flag. The value of this flag indicates the contents of the transmitter's buffer register[s] [SCITD/TDy] and shift register [SCITXSHF]. In multibuffer mode, this flag indicates the value of the TDx registers and shift register [SCITXSHF]. In non multibuffer mode, this flag indicates the value of LINTD0 [byte] and shift register [SCITXSHF]. This bit is set by: - RESET bit [SCIGCR0.0] - Setting the SWnRESET bit [SCIGCR1.7] - System reset. Note: This bit does not cause an interrupt request. 1 Compatible mode or LIN with no
multibuffer: |
| 10 | TXWAKE | R/W | 0h | SCI transmitter wakeup method select. This bit is effective in SCI-compatible mode only. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format. This bit is set to 1 or 0 by software before a byte is written to SCITD and is cleared by the SCI when data is transferred from SCITD to SCITXSHF or by a system reset. TXWAKE is not cleared by the SWnRESET bit [SCIGCR1.7]. 1 Address-bit mode: |
| 9 | RXRDY | R/W1TC | 0h | Receiver ready flag. In SCI compatibility mode, the receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU. In LIN mode, RXRDY is set once a valid frame is received in multibuffer mode, a valid frame being a message frame received with no errors. In non multibuffer mode RXRDY is set for each received byte and will be set for the last byte of the frame if there are no errors. The SCI/LIN generates a receive interrupt when RXRDY flag bit is set if the interrupt-enable bit is set [SCISETINT.9]. RXRDY is cleared by: - RESET bit [SCIGCR0.0] - Setting the SWnRESET - System reset - Writing a 1 to this bit - Reading SCIRD in while in SCI compatibility mode - Reading last data byte RDy of the response in LIN mode Note: The RXRDY flag cannot be cleared by Reading the corresponding interrupt offset in the SCIINTVECT0/1 register. 1 New data ready to be read from SCIRD. 0 No new data in SCIRD/RDy. |
| 8 | TXRDY | R | 1h | Transmitter buffer register ready flag. When set, this bit indicates that the transmit buffer[s] register [SCITD in compatibility mode and LINTD0, LINTD1 in MBUF mode] is/are ready to get another character from a CPU write. In SCI compatibility mode, Writing data to SCITD automatically clears this bit. In LIN mode, this bit is cleared once byte 0 [TD0] is written to LINTD0. This bit is set after the data of the TX buffer are shifted into the SCITXSHF register. This event can trigger a transmit DMA event if the DMA enable bit is set. This bit is set to 1 by: - RESET bit [SCIGCR0.0] - Setting the SWnRESET [SCIGCR1.7] - System reset Note: The TXRDY flag cannot be cleared by Reading the corresponding interrupt offset in the SCIINTVECT0/1 register. Note: The transmit interrupt request can be eliminated until the next series of data is written into the transmit buffers LINTD0 and LINTD1, by disaLINg the corresponding interrupt via the SCICLEARINT register or by disaLINg the transmitter via the TXENA bit [SCIGCR1.25=0]. 1 Compatible mode: SCITD is ready to receive
the next character. |
| 7 | TOA3WUS | R/W1TC | 0h | Timeout After 3 Wakeup Signals flag. This bit is effective in LIN mode only. This flag is set if there is no Sync Break received after 3 wakeup signals and a period of 1.5 seconds have passed. Such expiration time is used before issuing another round of wakeup signals. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit [SCIGCR1.7] - RESET bit [SCIGCR0.0] - System reset - Writing a 1 to this bit This field is writable in LIN mode only. 1 Timeout after 3 wakeup signals and 1.5s
time.
0 No timeout after 3 wakeup signals. |
| 6 | TOAWUS | R/W1TC | 0h | Timeout After Wakeup Signal flag. This bit is effective in LIN mode only. This bit is set if there is no Sync Break received after a wakeup signal has been sent. A minimum of 150 ms expiration time is used before issuing another wakeup signal. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit [SCIGCR1.7] - RESET bit [SCIGCR0.0] - System reset - Writing a 1 to this bit This field is writable in LIN mode only. 1 Timeout after one wakeup signal.
0 No timeout after one wakeup signal (150
ms). |
| 5 | RESERVED_1 | R | 0h | Reserved |
| 4 | TIMEOUT | R/W1TC | 0h | LIN Bus IDLE timeout flag. This bit is effective in LIN mode only. This bit is set if there is no LIN bus activity for at least 4 seconds. LIN bus activity being a transition from recessive to dominant. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit [SCIGCR1.7] - RESET bit [SCIGCR0.0] - System reset - Writing a 1 to this bit This field is writable in LIN mode only. 1 LIN bus idle detected. 0 No bus idle detected. |
| 3 | BUSY | R | 0h | Bus BUSY flag. This bit is effective in LIN mode and SCI-compatible mode. This bit indicates whether the receiver is in the process of receiving a frame. As soon as the receiver detects the beginning of a start bit, the BUSY bit is set to 1. When the reception of a frame is complete, the BUSY bit is cleared. If SET WAKEUP INT is set and power down is requested while this bit is set, the SCI/LIN automatically prevents low-power mode from being entered and generates wakeup interrupt. The BUSY bit is controlled directly by the SCI receiver but can be cleared by: - Setting the SWnRESET bit [SCIGCR1.7] - RESET bit [SCIGCR0.0] - System reset. 1 Receiver is currently receiving a frame.
0 Receiver is not currently receiving a
frame. |
| 2 | IDLE | R | 1h | SCI receiver in idle state. This bit is effective in SCI-compatible mode only. While this bit is set, the SCI looks for an idle period to resynchronize itself with the bit stream. The receiver does not receive any data while the bit is set. The bus must be idle for 11 bit periods to clear this bit. The SCI enters this state: - After a system reset - Setting the SWnRESET bit [SCIGCR1.7] - After coming out of power down This bit is writable in SCI mode only. 1 Idle period not detected, the SCI will not
receive any data.
0 Idle period detected, the SCI is ready to
receive. |
| 1 | WAKEUP | R/W1TC | 0h | Wake-up flag. This bit is effective in LIN mode only. This bit is set by the SCI/LIN when receiver or transmitter activity has taken the module out of power-down mode. An interrupt is generated if the SET WAKEUP INT bit [SCISETINT.1] is set. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register. - Setting the SWnRESET bit [SCIGCR1.7] - RESET bit [SCIGCR0.0] - System reset - Writing a 1 to this bit. This field is writable in LIN mode only. 1 Wake up from power-down mode. 0 Do not wake up from power-down mode. |
| 0 | BRKDT | R/W1TC | 0h | SCI break-detect flag. This bit is effective in SCI-compatible mode only. This bit is set when the SCI detects a break condition on the LINRX pin. A break condition occurs when the LINRX pin remains continuously low for at least 10 bits after a missing first stop bit, that is, after a framing error. Detection of a break condition causes the SCI to generate an error interrupt if the BRKDT INT ENA bit is set. The BRKDT bit is cleared by the following: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register. - Setting the SWnRESET bit [SCIGCR1.7] - RESET bit [SCIGCR0.0] - System reset - By Writing a 1 to this bit. This bit is writable in SCI mode only. 1 Break condition detected. 0 No break condition detected. |