SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.2.2.45 ADC_CFG_ADCCTL1 Register

2.2.45.1 ADC_CFG_ADCCTL1 Register (Offset = 0h) [reset = 0h]

ADC Control 1 Register.

Table 3-93 Instance Table

Instance Name	Physical Address
ADC0_G0_G5	502C 0000h
ADC1_G0_G5	502C 1000h
ADC2_G0_G5	502C 2000h
ADC3_G0_G5	502C 3000h
ADC4_G0_G5	502C 4000h

Figure 3-45 ADC_CFG_ADCCTL1 Name Register

15	14	13	12	11	10	9	8
TDMAEN	EXTMUXPRESELECTEN	ADCBSY	RESERVED_3	ADCBSYCHN
R/W	R/W	R	R	R
0h	0h	0h	0h	0h
7	6	5	4	3	2	1	0
ADCPWDNZ	RESERVED_2				INTPULSEPOS	RESERVED_1
R/W	R				R/W	R
0h	0h				0h	0h

Table 3-94 ADC_CFG_ADCCTL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	TDMAEN	R/W	0h	Enable Alternate DMA Timings. This bit controls when the DMA is triggered. 0 DMA is triggered at the same time as the CPU interrupt 1 DMA is always triggered at tDMA regardless or whether the ADC is in early interrupt mode or late interrupt mode
14	EXTMUXPRESELECTEN	R/W	0h	If th the ADC SOC sequence is deterministic, the ADCEXTMUX pins can be set earlier: at the end of the S+H window of the previous conversion instead of the beginning of the S+H window of the current conversion. This allows some of the external mux settling time to be pipelined with the previous conversion's conversion time. However, this will not work in the case where high-priority SOCs can arrive asynchronously. 0 ADCEXTMUX pins only change at beginning of S+H window 1 ADCEXTMUX pins are set after the end of S+H window based on pending SOCs
13	ADCBSY	R	0h	ADC Busy. Set when ADC SOC is generated, cleared by hardware four ADC clocks after negative edge of S/H pulse. Used by the ADC state machine to determine if ADC is available to sample. 0 ADC is available to sample next channel 1 ADC is busy and cannot sample another channel
12	RESERVED_3	R	0h	Reserved
11:8	ADCBSYCHN	R	0h	ADC Busy Channel. Set when an ADC Start of Conversion [SOC] is generated. When ADCBSY 0:holds the value of the last converted SOC When ADCBSY 1:reflects the SOC currently being processed 0h SOC0 is currently processing or was last SOC converted 1h SOC1 is currently processing or was last SOC converted 2h SOC2 is currently processing or was last SOC converted 3h SOC3 is currently processing or was last SOC converted 4h SOC4 is currently processing or was last SOC converted 5h SOC5 is currently processing or was last SOC converted 6h SOC6 is currently processing or was last SOC converted 7h SOC7 is currently processing or was last SOC converted 8h SOC8 is currently processing or was last SOC converted 9h SOC9 is currently processing or was last SOC converted Ah SOC10 is currently processing or was last SOC converted Bh SOC11 is currently processing or was last SOC converted Ch SOC12 is currently processing or was last SOC converted Dh SOC13 is currently processing or was last SOC converted Eh SOC14 is currently processing or was last SOC converted Fh SOC15 is currently processing or was last SOC converted
7	ADCPWDNZ	R/W	0h	ADC Power Down [active low]. This bit controls the power up and power down of all the analog circuitry inside the analog core. 0 All analog circuitry inside the core is powered down 1 All analog circuitry inside the core is powered up
6:3	RESERVED_2	R	0h	Reserved
2	INTPULSEPOS	R/W	0h	ADC Interrupt Pulse Position. 0 Interrupt pulse generation occurs when ADC begins conversion [at the end of the acquisition window] plus a number of SYSCLK cycles as specified in the ADCINTCYCLE.OFFSET register. 1 Interrupt pulse generation occurs at the end of the conversion, 1 cycle prior to the ADC result latching into its result register
1:0	RESERVED_1	R	0h	Reserved