SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.2.46.1 ADC_CFG_ADCCTL2 Register (Offset = 2h) [reset = 0h]

ADC Control 2 Register.

Table 3-95 Instance Table

Figure 3-46 ADC_CFG_ADCCTL2 Name Register

Table 3-96 ADC_CFG_ADCCTL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15:13	RESERVED_3	R	0h	Reserved
12:9	RESERVED_2	R	0h	Reserved
8	OFFTRIMMODE	R/W	0h	ADC offset trim mode. 0 = Offset trim supplied by ADCOFFTRIM.OFFTRIM regardless of resolution or signal mode 1 = Offset trim for each combination of resolution, signalmode, and even or odd is supplied by a different field in ADCOFFTRIM, ADCOFFTRIM2, or ADCOFFTRIM3
7	SIGNALMODE	R/W	0h	SOC Signaling Mode. Selects the input mode of the converter. Use the AdcSetMode function to change the signal mode. 0 Single-ended 1 Differential
6	RESOLUTION	R/W	0h	SOC Conversion Resolution. Selects the resolution of the converter. Use the AdcSetMode function to change the resolution. 0 12-bit resolution 1 16-bit resolution. Note: 16-bit resolution is not supported.
5:4	RESERVED_1	R	0h	Reserved
3:0	PRESCALE	R/W	0h	ADC Clock Prescaler. 0000 ADCCLK = Input Clock / 1.0 0001 Invalid 0010 ADCCLK = Input Clock / 2.0 0011 ADCCLK = Input Clock / 2.5 0100 ADCCLK = Input Clock / 3.0 0101 ADCCLK = Input Clock / 3.5 0110 ADCCLK = Input Clock / 4.0 0111 ADCCLK = Input Clock / 4.5 1000 ADCCLK = Input Clock / 5.0 1001 ADCCLK = Input Clock / 5.5 1010 ADCCLK = Input Clock / 6.0 1011 ADCCLK = Input Clock / 6.5 1100 ADCCLK = Input Clock / 7.0 1101 ADCCLK = Input Clock / 7.5 1110 ADCCLK = Input Clock / 8.0 1111 ADCCLK = Input Clock / 8.5