SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.2.2.47 ADC_CFG_ADCBURSTCTL Register

2.2.47.1 ADC_CFG_ADCBURSTCTL Register (Offset = 4h) [reset = 0h]

ADC Burst Control Register.

Table 3-97 Instance Table

Instance Name	Physical Address
ADC0_G0_G5	502C 0004h
ADC1_G0_G5	502C 1004h
ADC2_G0_G5	502C 2004h
ADC3_G0_G5	502C 3004h
ADC4_G0_G5	502C 4004h

Figure 3-47 ADC_CFG_ADCBURSTCTL Name Register

15	14	13	12	11	10	9	8
BURSTEN	RESERVED_2			BURSTSIZE
R/W	R			R/W
0h	0h			0h
7	6	5	4	3	2	1	0
RESERVED_1	BURSTTRIGSEL
R	R/W
0h	0h

Table 3-98 ADC_CFG_ADCBURSTCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	BURSTEN	R/W	0h	SOC Burst Mode Enable. This bit enables the SOC Burst Mode of operation. 0 Burst mode is disabled. 1 Burst mode is enabled.
14:12	RESERVED_2	R	0h	Reserved
11:8	BURSTSIZE	R/W	0h	SOC Burst Size Select. This bit field determines how many SOCs are converted when a burst conversion sequence is started. The first SOC converted is defined by the round robin pointer, which is advanced as each SOC is converted. 0h 1 SOC converted 1h 2 SOCs converted 2h 3 SOCs converted 3h 4 SOCs converted 4h 5 SOCs converted 5h 6 SOCs converted 6h 7 SOCs converted 7h 8 SOCs converted 8h 9 SOCs converted 9h 10 SOCs converted Ah 11 SOCs converted Bh 12 SOCs converted Ch 13 SOCs converted Dh 14 SOCs converted Eh 15 SOCs converted Fh 16 SOCs converted Note: If the burst causes SOCs to be set for conversion that were already pending, the corresponding bits in the ADCSOCOVF register will be set.
7	RESERVED_1	R	0h	Reserved
6:0	BURSTTRIGSEL	R/W	0h	SOC Burst Trigger Source Select. Configures which trigger will start a burst conversion sequence. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h BURSTTRIG0 - Software only 01h BURSTTRIG1 - RTI0 Timer 02h BURSTTRIG2 - RTI1 Timer 03h BURSTTRIG3 - RTI2 Timer 04h BURSTTRIG4 - RTI3 Timer 05h BURSTTRIG5 - InputXBAR.Out[5] 06h BURSTTRIG6 - spare 07h BURSTTRIG7 - spare 08h BURSTTRIG8 - EPWM0, ADCSOCA 09h BURSTTRIG9 - EPWM0, ADCSOCB 0Ah BURSTTRIG10 - EPWM1, ADCSOCA 0Bh BURSTTRIG11 - EPWM1, ADCSOCB 0Ch BURSTTRIG12 - EPWM2, ADCSOCA 0Dh BURSTTRIG13 - EPWM2, ADCSOCB 0Eh BURSTTRIG14 - EPWM3, ADCSOCA 0Fh BURSTTRIG15 - EPWM3, ADCSOCB .... EPWM4 to EPWM27 40h BURSTTRIG64 - EPWM28, ADCSOCA 41h BURSTTRIG65 - EPWM28, ADCSOCB 42h BURSTTRIG66 - EPWM29, ADCSOCA 43h BURSTTRIG67 - EPWM29, ADCSOCB 44h BURSTTRIG68 - EPWM30, ADCSOCA 45h BURSTTRIG69 - EPWM30, ADCSOCB 46h BURSTTRIG70 - EPWM31, ADCSOCA 47h BURSTTRIG71 - EPWM31, ADCSOCB 48h BURSTTRIG72 - ECAP0, TRIGOUT .... ECAP1 to ECAP8 51h BURSTTRIG81 - ECAP9, TRIGOUT 52h BURSTTRIG82 - ECAP10, TRIGOUT .... 57h BURSTTRIG73 - ECAP15, TRIGOUT 58h BURSTTRIG1 - RTI4 Timer 59h BURSTTRIG1 - RTI5 Timer 5Ah BURSTTRIG1 - RTI6 Timer 5Bh BURSTTRIG1 - RTI7 Timer .... 7Eh BURSTTRIG126 - REP1TRIG - these are not external trigger signals on the ADC IP port. We need to configure them for internal selection of repeater triggers. 7Fh BURSTTRIG127 - REP2TRIG - these are not external trigger signals on the ADC IP port. We need to configure them for internal selection of repeater triggers.