SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
ADC Event Clear Register.
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| Instance Name | Physical Address |
|---|---|
| ADC0_G0_G5 | 502C 0064h |
| ADC1_G0_G5 | 502C 1064h |
| ADC2_G0_G5 | 502C 2064h |
| ADC3_G0_G5 | 502C 3064h |
| ADC4_G0_G5 | 502C 4064h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_4 | PPB4ZERO | PPB4TRIPLO | PPB4TRIPHI | RESERVED_3 | PPB3ZERO | PPB3TRIPLO | PPB3TRIPHI |
| R | R/W1TS | R/W1TS | R/W1TS | R | R/W1TS | R/W1TS | R/W1TS |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED_2 | PPB2ZERO | PPB2TRIPLO | PPB2TRIPHI | RESERVED_1 | PPB1ZERO | PPB1TRIPLO | PPB1TRIPHI |
| R | R/W1TS | R/W1TS | R/W1TS | R | R/W1TS | R/W1TS | R/W1TS |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED_4 | R | 0h | Reserved |
| 14 | PPB4ZERO | R/W1TS | 0h | Post Processing Block 4 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority |
| 13 | PPB4TRIPLO | R/W1TS | 0h | Post Processing Block 4 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority |
| 12 | PPB4TRIPHI | R/W1TS | 0h | Post Processing Block 4 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority |
| 11 | RESERVED_3 | R | 0h | Reserved |
| 10 | PPB3ZERO | R/W1TS | 0h | Post Processing Block 3 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority |
| 9 | PPB3TRIPLO | R/W1TS | 0h | Post Processing Block 3 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority |
| 8 | PPB3TRIPHI | R/W1TS | 0h | Post Processing Block 3 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority |
| 7 | RESERVED_2 | R | 0h | Reserved |
| 6 | PPB2ZERO | R/W1TS | 0h | Post Processing Block 2 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority |
| 5 | PPB2TRIPLO | R/W1TS | 0h | Post Processing Block 2 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority |
| 4 | PPB2TRIPHI | R/W1TS | 0h | Post Processing Block 2 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority |
| 3 | RESERVED_1 | R | 0h | Reserved |
| 2 | PPB1ZERO | R/W1TS | 0h | Post Processing Block 1 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority |
| 1 | PPB1TRIPLO | R/W1TS | 0h | Post Processing Block 1 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority |
| 0 | PPB1TRIPHI | R/W1TS | 0h | Post Processing Block 1 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register. Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority |