SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
ADC Trigger Repeater 2 Phase Select Register.
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| Instance Name | Physical Address |
|---|---|
| ADC0_G0_G5 | 502C 0128h |
| ADC1_G0_G5 | 502C 1128h |
| ADC2_G0_G5 | 502C 2128h |
| ADC3_G0_G5 | 502C 3128h |
| ADC4_G0_G5 | 502C 4128h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHASECOUNT | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHASECOUNT | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHASE | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHASE | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | PHASECOUNT | R | 0h | ADC trigger repeater 2 phase delay status. When the trigger selected by REP2CTL.TRIGSEL is received, this register will start counting down from PHASECOUNT until the counter reaches 0, at which point the trigger will be passed on to the repeater re-trigger logic. If the trigger selected by REP2CTL.TRIGSEL is recieved when PHASECOUNT is not 0 [the phase delay logic is busy from the previous trigger] then the new trigger will be ignored and REP2CTL.PHASEOVF will be set to 1. |
| 15:0 | PHASE | R/W | 0h | ADC trigger repeater 2 phase delay configuration. Defines the number of SYSCLKs to delay the selected trigger before passing it on to the re-triggering logic. 0 = trigger is passed through without delay 1 = trigger is delayed by 1 SYSCLK 2 = trigger is delayed by 2 SYSCLKs ... 65535 = trigger is delayed by 65535 SYSCLKs |