SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.2.2.160 ADC_CFG_ADCPPB4CONFIG2 Register

2.2.160.1 ADC_CFG_ADCPPB4CONFIG2 Register (Offset = 1E4h) [reset = 0h]

ADC PPB4 Sum Shift Register.

Table 3-323 Instance Table

Instance Name	Physical Address
ADC0_G0_G5	502C 01E4h
ADC1_G0_G5	502C 11E4h
ADC2_G0_G5	502C 21E4h
ADC3_G0_G5	502C 31E4h
ADC4_G0_G5	502C 41E4h

Figure 3-160 ADC_CFG_ADCPPB4CONFIG2 Name Register

15	14	13	12	11	10	9	8
COMPSEL		RESERVED_2	OSINTSEL	SWSYNC	RESERVED_1	SYNCINSEL
R/W		R	R/W	R/W1TS	R	R/W
0h		0h	0h	0h	0h	0h
7	6	5	4	3	2	1	0
SYNCINSEL				SHIFT
R/W				R/W
0h				0h

Table 3-324 ADC_CFG_ADCPPB4CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15:14	COMPSEL	R/W	0h	Post Processing Block 4 Compare Source Select. This field determines whether ADCPPB4RESULT, ADCPPB4PSUM, or ADCPPB4SUM is used for the zero-crossing detect logic and threshold compare. 00 = ADCPPB4RESULT is used for compare logic 01 = ADCPPB4PSUM is used for compare logic 10 = ADCPPB4SUM is used for compare logic 11 = Reserved Note: when ADCPPB4PSUM is selected as the compare source and when a LIMIT match occurs [ADCPPB4LIMIT equals ADCPPB4COUNT] the ADCPPB4PSUM register will be cleared and the final sum will be loaded into ADCPPB4SUM. For this sample, the final sum, ADCPPB4SUM will be used for the compariosn instead of ADCPPB4PSUM.
13	RESERVED_2	R	0h	Reserved
12	OSINTSEL	R/W	0h	Post Processing Block 4 Interrupt Source Select. OSINT4 can be used to trigger an ADC interrupt [ADCINT1 through ADCINT4] via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT4 in addition to a PCOUNT = LIMIT event. 0 = OSINT4 will be generated from PCOUNT = LIMIT only 1 = OSTIN4 will be generated form PCOUNT = LIMIT or a sync. event. Note: If a SYNC event would cause an OSINT one cycle after OSINT would have been cause by PCOUNT = LIMIT match, then the second OSINT is ignored.
11	SWSYNC	R/W1TS	0h	PPB 4 software force sync. On a sync. event, all partial registers transfer to the final registers and are then reset. Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is being used for a high or low limit compare, then the comparison will not occur.
10	RESERVED_1	R	0h	Reserved
9:4	SYNCINSEL	R/W	0h	PPB 4 sync. input select. On a sync. event, all partial registers transfer to the final registers and are then reset.
3:0	SHIFT	R/W	0h	Post Processing Block 4 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM. 0 : no right shift 1 : SUM = PSUM '' 1 2 : SUM = PSUM '' 2 ... 10 : SUM = PSUM '' 10 11 - 15 : Reserved