SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.2.161.1 ADC_CFG_ADCPPB4PSUM Register (Offset = 1E8h) [reset = 0h]

ADC PPB4 Partial Sum Register.

Table 3-325 Instance Table

Figure 3-161 ADC_CFG_ADCPPB4PSUM Name Register

Table 3-326 ADC_CFG_ADCPPB4PSUM Register Field Descriptions

Bit	Field	Type	Reset	Description
31:24	SIGN	R	0h	Sign Extended Bits. These bits reflect the same value as bit 23.
23:0	PSUM	R	0h	Post Processing Block 4 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result is subsequently accumulated into this register. This register is reset when either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event. This result is available 1 SYSCLK cycle after the associated ADCPPB4RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC. In the case of multiple PPBs associated with the same SOC, the lowest numbered PPB's result will be availble 2 SYSCLK cycle after the associated ADCRESULT and subsequent results [in order from lowest numbered PPB to highest] will each become available every 2-3 SYSCLK cycles [refer to the TRM for detailed timing information].