SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

10.2.1.1 FSI_TX_CFG_TX_MASTER_CTRL Register (Offset = 0h) [reset = 0h]

Transmit master control register.

Table 3-1068 Instance Table

Figure 3-502 FSI_TX_CFG_TX_MASTER_CTRL Name Register

Table 3-1069 FSI_TX_CFG_TX_MASTER_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15:8	KEY	W	0h	Write Key In order to write to any bit in this register, 0xA5 must be written to this field at the same time. Otherwise, writes are ignored. The key is cleared immediately after Writing, so it must be written again for every change to this register.
7:2	RESERVED_1	R	0h	Reserved
1	FLUSH	R/W	0h	Flush Operation Start bit This bit will cause the transmitter to initiate a flush pattern of a single toggle on the TXD0 and TXD1 followed by five full cycles of TXCLK. This bit should be written only when the CORE_RST bit is 0 and the clock to the Transmitter core is turned on. 0h[R/W] = Clear this bit. 1h[R/W] = Setting this bit will Initiate flush sequence. To properly execute a flush sequence, Set FLUSH to 1, wait for five TXCLK cycles then clear FLUSH to 0. Note: The KEY field must contain 0xA5 for any write to this bit to take effect. The software must keep this bit set to 1 for at least five TXCLK cycles before setting it back to 0.
0	CORE_RST	R/W	0h	Transmitter Master Core Reset bit This bit controls the transmitter master core reset. In order to send any frame, this bit must be cleared. 0h[R/W] = Transmitter core is not in reset and can transmit frames. 1h[R/W] = Transmitter core is held in reset. Note: The KEY field must contatin 0xA5 for any write to this bit to take effect.