SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

10.2.2.1 FSI_TX_CFG_TX_CLK_CTRL Register (Offset = 4h) [reset = 0h]

Transmit clock control register.

Table 3-1070 Instance Table

Figure 3-503 FSI_TX_CFG_TX_CLK_CTRL Name Register

Table 3-1071 FSI_TX_CFG_TX_CLK_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15:10	RESERVED_1	R	0h	Reserved
9:2	PRESCALE_VAL	R/W	0h	Clock Divider Prescale Value The input clock is divided by this 8-bit value and fed into the transmitter core. This divided clock is the rate at which TXCLK will operate. 0h[R/W] = Reserved 1h[R/W] = Input clock /1 2h[R/W] = Input clock /2 3h[R/W] = Input clock /3 4h[R/W] = Input clock /4 ... FFh [R/W] = Input clock /255 TXCLKIN = Input clock / PRESCALE_VAL In FSI mode: TXCLK = TXCLKIN / 2 In SPI mode: TXCLK = TXCLKIN
1	CLK_EN	R/W	0h	Clock Divider Enable bit This bit will enable and disable the input clock divider and start the clock to the transmitter core. 0h[R/W] = The input clock divider is not enabled and the clock is not connected to the transmitter core. 1h[R/W] = The input clock to the transmitter core is being divided by the PRESCALE_VAL and enabled.
0	CLK_RST	R/W	0h	Clock Divider Reset bit This bit will reset the clock counter in the clock divider. 0h[R/W] = The clock divider is set based on the value in PRESCALE_VAL. The input clock will be divided by PRESCALE_VAL if CLK_EN is set. 1h[R/W] = The clock divider will be reset to 0 and will stay reset until software writes a 0 to this bit.