SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.10.2.3 FSI_TX_CFG_TX_OPER_CTRL_LO_ALT2 Register

10.2.3.1 FSI_TX_CFG_TX_OPER_CTRL_LO_ALT2 Register (Offset = 8h) [reset = 0h]

Transmit operation control register low.

Table 3-1072 Instance Table

Instance Name	Physical Address
FSI_TX0	5028 0008h
FSI_TX1	5028 1008h
FSI_TX2	502A 0008h
FSI_TX3	502A 1008h

Figure 3-504 FSI_TX_CFG_TX_OPER_CTRL_LO_ALT2 Name Register

15	14	13	12	11	10	9	8
RESERVED_1					SEL_TDM_IN	TDM_ENABLE	SEL_PLLCLK
R					R/W	R/W	R/W
0h					0h	0h	0h
7	6	5	4	3	2	1	0
PING_TO_MODE	SW_CRC	START_MODE			SPI_MODE	DATA_WIDTH
R/W	R/W	R/W			R/W	R/W
0h	0h	0h			0h	0h

Table 3-1073 FSI_TX_CFG_TX_OPER_CTRL_LO_ALT2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15:11	RESERVED_1	R	0h	Reserved
10	SEL_TDM_IN	R/W	0h	Input TDM port Select bit This bit selects the input port for the transmitter core between the TDM input pins or the RX module. When this bit is '0', the inputs selected for TDM are from the TDM input pins. When this bit is '1', then inputs selected for TDM are from the RX module.
9	TDM_ENABLE	R/W	0h	Transmit TDM Mode Enable bit. This bit enables the TDM Mode for multi-target TDM operation. 0h[R/W] Transmit TDM Mode is not enabled. 1h[R/W] Transmit TDM Mode is enabled.
8	SEL_PLLCLK	R/W	0h	Input Clock Select bit This bit selects the input clock source for the transmitter core. 0h[R/W] = SYSCLK is the source of the transmitter clock into the clock prescaler. 1h[R/W] = PLLRAWCLK is the source of the transmitter core clock into the clock prescaler.
7	PING_TO_MODE	R/W	0h	Ping Counter Reset Mode Select bit This bit selects when the ping counter will reset. 0h[R/W] = The ping counter will reset and restart only on hardware initiated ping frames, when ping counter has timed out. 1h[R/W] = The ping counter will reset and restart on any software initiated frame as well as a ping counter timeout
6	SW_CRC	R/W	0h	CRC Source Select bit This bit selects the source of the CRC value that is transmitted. 0h[R/W] = The transmitted CRC value is computed by hardware. 1h[R/W] = The transmitted CRC value is sourced from the value programmed in the TX_USER_CRC register.
5:3	START_MODE	R/W	0h	Transmission Start Mode Select bit These bits select the method by which a new frame transmission is started. 0h[R/W] = Only a software write to TX_FRAME_CTRL.START initiate a new transmission. 1h[R/W] = The configured external trigger will initiate a new transmission. 2h[R/W] = Either Writing to TX_FRAME_CTRL.START or the TX_FRAME_TAG_UDATA register will initiate a new transmission. All other combinations of bits are illegal and reserved for future use.
2	SPI_MODE	R/W	0h	SPI Mode Select bit This bit enables and disables SPI compatibility mode. 0h[R/W] = FSI is in normal mode of operation. 1h[R/W] = FSI is operating in SPI compatibility mode.
1:0	DATA_WIDTH	R/W	0h	Transmit Data Width Select bits These bits define the number of data lines used by the transmitter. 0h[R/W] = Data will be transmitted on one data line [TXD0] 1h[R/W] = Data will be transmitted on two data lines [TXD0 and TXD1]. The format of the data is described in the FSI_TX TRM chapter. 2h 3h[R/W] = Reserved