SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Transmit event and error status flag register.
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| Instance Name | Physical Address |
|---|---|
| FSI_TX0 | 5028 0028h |
| FSI_TX1 | 5028 1028h |
| FSI_TX2 | 502A 0028h |
| FSI_TX3 | 502A 1028h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_1 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED_1 | PING_TRIGGERED | BUF_OVERRUN | BUF_UNDERRUN | FRAME_DONE | |||
| R | R | R | R | R | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:4 | RESERVED_1 | R | 0h | Reserved |
| 3 | PING_TRIGGERED | R | 0h | Ping Frame Triggered Flag Bit This bit indicates that a ping frame has been triggered. This bit is set by hardware when either the ping timer or an external trigger event have occured. Software can also force this bit to get set by Writing to the TX_EVT_FRC register. 0h[R] = A ping frame has not been triggered. 1h[R] = A ping frame has been triggered by either the ping timer or external trigger. To clear this bit, write to the corresponding bit in the TX_EVT_CLR register. |
| 2 | BUF_OVERRUN | R | 0h | Buffer Overrun Flag Bit This bit inditcates that buffer overrun has occured.Software can also force this bit to get set by Writing to the TX_EVT_FRC register. 0h[R] = Buffer Overrun has not occured. 1h[R] = Buffer Overrun has occured. To clear this bit, write to the corresponding bit in the TX_EVT_CLR register. |
| 1 | BUF_UNDERRUN | R | 0h | Buffer Underrun Flag Bit This bit inditcates that buffer underrun has occured.Software can also force this bit to get set by Writing to the TX_EVT_FRC register. 0h[R] = Buffer Underrun has not occured. 1h[R] = Buffer Underrun has occured. To clear this bit, write to the corresponding bit in the TX_EVT_CLR register. |
| 0 | FRAME_DONE | R | 0h | Frame Done Flag Bit This bit inditcates a Frame Done condition. This bit is set by hardware when a frame transmission has been completed. Software can also force this bit to get set by Writing to the TX_EVT_FRC register. 0h[R] = Frame Done condition has not occured. 1h[R] = Frame Done condition has occured. To clear this bit, write to the corresponding bit in the TX_EVT_CLR register. |