SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Pin control Register 4
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| Instance Name | Physical Address |
|---|---|
| LIN0 | 5240 004Ch |
| LIN1 | 5240 104Ch |
| LIN2 | 5240 204Ch |
| LIN3 | 5240 304Ch |
| LIN4 | 5240 404Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_3 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_3 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_2 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED_2 | TXSET | RXSET | RESERVED_1 | ||||
| R | R/W1TS | R/W1TS | R | ||||
| 0h | 0h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED_3 | R | 0h | Reserved |
| 15:3 | RESERVED_2 | R | 0h | Reserved |
| 2 | TXSET | R/W1TS | 0h | Transmit pin set. This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINTX. |
| 1 | RXSET | R/W1TS | 0h | Receive pin set. This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINRX. |
| 0 | RESERVED_1 | R | 0h | Reserved |