SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.11.2.34 LIN_IODFTCTRL Register

11.2.34.1 LIN_IODFTCTRL Register (Offset = 90h) [reset = 500h]

The IODFTCTRL register is used to emulate various error and test conditions.

Table 5-1358 Instance Table

Instance Name	Physical Address
LIN0	5240 0090h
LIN1	5240 1090h
LIN2	5240 2090h
LIN3	5240 3090h
LIN4	5240 4090h

Figure 5-672 LIN_IODFTCTRL Name Register

31	30	29	28	27	26	25	24
BERRENA	PBERRENA	CERRENA	ISFERRENA	RESERVED_4	FERRENA	PERRENA	BRKDTERRENA
R/W	R/W	R/W	R/W	R	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h
23	22	21	20	19	18	17	16
RESERVED_3			PINSAMPLEMASK		TXSHIFT
R/W			R/W		R/W
0h			0h		0h
15	14	13	12	11	10	9	8
RESERVED_2				IODFTENA
R				R/W
0h				5h
7	6	5	4	3	2	1	0
RESERVED_1						LPBENA	RXPENA
R						R/W	R/W
0h						0h	0h

Table 5-1359 LIN_IODFTCTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BERRENA	R/W	0h	Bit Errror Enable bit. This bit is effective in LIN mode only. This bit is used to create a Bit error. When this bit is set, the bit received is ORed with 1 and passed to the Bit monitor circuitry.
30	PBERRENA	R/W	0h	Physical Bus Error Enable bit. This bit is effective in LIN mode only. This bit is used to create a Physical Bus Error. When this bit is set, the bit received during Sync Break field transmission is ORed with 1 and passed to the Bit monitor circuitry
29	CERRENA	R/W	0h	Checksum Error Enable bit. This bit is effective in LIN mode only. This bit is used to create a checksum error. When this bit is set, the polarity of the CTYPE [checksum type] in the receive checksum calculator is changed so that a checksum error is generated.
28	ISFERRENA	R/W	0h	Inconsistent Sync Field Error Enable bit. This bit is effective in LIN mode only. This bit is used to create an ISF error. When this bit is set, the bit widths in the sync field are varied so that the ISF check fails and the error flag is set.
27	RESERVED_4	R	0h	Reserved
26	FERRENA	R/W	0h	This bit is used to create a Frame Error. This bit is effective in SCI-compatible mode only. When this bit is set, the stop bit received is ANDed with '0' and passed to the stop bit check circuitry.
25	PERRENA	R/W	0h	Compatible Mode only This bit is effective in SCI-compatible mode only. This bit is used to create a Parity Error. When this bit is set, in compatible mode, the parity bit received is toggled so that a parity error occurs.
24	BRKDTERRENA	R/W	0h	Compatible Mode only This bit is effective in SCI-compatible mode only. This bit is used to create BRKDT error [SCI mode only]. When this bit is set, the stop bit of the frame is ANDed with '0' and passed to the RSM so that a frame error occurs. Then the RX Pin is forced to continuous low for 10 Tbits so that a BRKDT error occurs.
23:21	RESERVED_3	R/W	0h	Reserved
20:19	PINSAMPLEMASK	R/W	0h	Pin sample mask. These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples correctly with the majority detection circuitry. Note: During IODFT mode testing for the pin sample mask, the prescalar P must be programmed to be greater than 2. 3 Invert the TX Pin value at TBIT_CENTER + 2 SCLK 2 Invert the TX Pin value at TBIT_CENTER + SCLK 1 Invert the TX Pin value at TBIT_CENTER 0 No Mask
18:16	TXSHIFT	R/W	0h	Transmit shift. These bits define the delay by which the value on LINTX is delayed so that the value on LINRX is asynchronous. [Not applicable to Start Bit] 7 Delay by 7 SCLK 6 Delay by 6 SCLK 5 Delay by 5 SCLK 4 Delay by 4 SCLK 3 Delay by 3 SCLK 2 Delay by 2 SCLK 1 Delay by 1 SCLK 0 No Delay
15:12	RESERVED_2	R	0h	Reserved
11:8	IODFTENA	R/W	5h	IO DFT Enable Key This field is used to enable the IODFT mode of the SCI/LIN module for testing. 15 IODFT is disabled 14 IODFT is disabled 13 IODFT is disabled 12 IODFT is disabled 11 IODFT is disabled 10 IODFT is enabled 9 IODFT is disabled 8 IODFT is disabled 7 IODFT is disabled 6 IODFT is disabled 5 IODFT is disabled 4 IODFT is disabled 3 IODFT is disabled 2 IODFT is disabled 1 IODFT is disabled 0 IODFT is disabled
7:2	RESERVED_1	R	0h	Reserved
1	LPBENA	R/W	0h	Module loopback enable. In analog loopback mode the complete communication path through the I/Os can be tested, whereas in digital loopback mode the I/O buffers are excluded from this path. 1 Analog loopback is enabled in module I/O DFT mode (when IODFTENA = 1010) 0 Digital loopback is enabled.
0	RXPENA	R/W	0h	Module Analog loopback through receive pin enable. This bit defines whether the I/O buffers for the transmit or the receive pin are included in the communication path in analog loopback mode only. 1 Analog loopback through the receive pin is enabled. 0 Analog loopback through the transmit pin is enabled.