SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.13.2.1 MSS_MCRC_CRC_CTRL0 Register

13.2.1.1 MSS_MCRC_CRC_CTRL0 Register (Offset = 0h) [reset = 0h]

Contains sw reset control bit to reset PSA.

Table 5-1571 Instance Table

Instance Name	Physical Address
MCRC0	3500 0000h

Figure 5-775 MSS_MCRC_CRC_CTRL0 Name Register

31	30	29	28	27	26	25	24
CH4_CRC_SEL2	CH4_BYTE_SWAP	CH4_BIT_SWAP	CH4_CRC_SEL		CH4_DW_SEL		CH4_PSA_SWREST
R/W	R/W	R/W	R/W		R/W		R/W
0h	0h	0h	0h		0h		0h
23	22	21	20	19	18	17	16
CH3_CRC_SEL2	CH3_BYTE_SWAP	CH3_BIT_SWAP	CH3_CRC_SEL		CH3_DW_SEL		CH3_PSA_SWREST
R/W	R/W	R/W	R/W		R/W		R/W
0h	0h	0h	0h		0h		0h
15	14	13	12	11	10	9	8
CH2_CRC_SEL2	CH2_BYTE_SWAP	CH2_BIT_SWAP	CH2_CRC_SEL		CH2_DW_SEL		CH2_PSA_SWREST
R/W	R/W	R/W	R/W		R/W		R/W
0h	0h	0h	0h		0h		0h
7	6	5	4	3	2	1	0
CH1_CRC_SEL2	CH1_BYTE_SWAP	CH1_BIT_SWAP	CH1_CRC_SEL		CH1_DW_SEL		CH1_PSA_SWREST
R/W	R/W	R/W	R/W		R/W		R/W
0h	0h	0h	0h		0h		0h

Table 5-1572 MSS_MCRC_CRC_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CH4_CRC_SEL2	R/W	0h	Refer "CH4_DW_SEL" field description
30	CH4_BYTE_SWAP	R/W	0h	BYTE SWAP Enable across Data Size 0 Byte Swap Disabled 1 Byte Swap enabled.
29	CH4_BIT_SWAP	R/W	0h	msb/lsb SWAPPING 0 msb [most significant bit First] 1 lsb [least significant bit First]
28:27	CH4_CRC_SEL	R/W	0h	CRC type select. {CH1_CRC_SEL2,CH1_CRC_SEL[1:0]} 000 CRC-64 001 - CRC-16 010 CRC-32 100 - VDA CAN, SAE-J1850 CRC-8 101 - H2F, Autosar 4.0 110 - CASTAGNOLI, iSCSI 111 / 011 - E2E Profile 4
26:25	CH4_DW_SEL	R/W	0h	CRC Data Size select. 000 64 bit Data Size 001 - 16 bit Data Size 010 32 Bit Data Size
24	CH4_PSA_SWREST	R/W	0h	Channel 4 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore, CPU is required to clear this bit by Writing a 0. 0 = PSA Signature Register not reset 1 = PSA Signature Register reset
23	CH3_CRC_SEL2	R/W	0h	Refer "CH3_DW_SEL" field description
22	CH3_BYTE_SWAP	R/W	0h	BYTE SWAP Enable across Data Size 0 Byte Swap Disabled 1 Byte Swap enabled.
21	CH3_BIT_SWAP	R/W	0h	msb/lsb SWAPPING 0 msb [most significant bit First] 1 lsb [least significant bit First]
20:19	CH3_CRC_SEL	R/W	0h	CRC type select. {CH1_CRC_SEL2,CH1_CRC_SEL[1:0]} 000 CRC-64 001 - CRC-16 010 CRC-32 100 - VDA CAN, SAE-J1850 CRC-8 101 - H2F, Autosar 4.0 110 - CASTAGNOLI, iSCSI 111 / 011 - E2E Profile 4
18:17	CH3_DW_SEL	R/W	0h	CRC Data Size select. 000 64 bit Data Size 001 - 16 bit Data Size 010 32 Bit Data Size
16	CH3_PSA_SWREST	R/W	0h	Channel 3 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore, CPU is required to clear this bit by Writing a 0. 0 = PSA Signature Register not reset 1 = PSA Signature Register reset
15	CH2_CRC_SEL2	R/W	0h	Refer "CH2_DW_SEL" field description
14	CH2_BYTE_SWAP	R/W	0h	BYTE SWAP Enable across Data Size 0 Byte Swap Disabled 1 Byte Swap enabled.
13	CH2_BIT_SWAP	R/W	0h	msb/lsb SWAPPING 0 msb [most significant bit First] 1 lsb [least significant bit First]
12:11	CH2_CRC_SEL	R/W	0h	CRC type select. {CH1_CRC_SEL2,CH1_CRC_SEL[1:0]} 000 CRC-64 001 - CRC-16 010 CRC-32 100 - VDA CAN, SAE-J1850 CRC-8 101 - H2F, Autosar 4.0 110 - CASTAGNOLI, iSCSI 111 / 011 - E2E Profile 4
10:9	CH2_DW_SEL	R/W	0h	CRC Data Size select. 000 64 bit Data Size 001 - 16 bit Data Size 010 32 Bit Data Size
8	CH2_PSA_SWREST	R/W	0h	Channel 2 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore, CPU is required to clear this bit by Writing a 0. 0 = PSA Signature Register not reset 1 = PSA Signature Register reset
7	CH1_CRC_SEL2	R/W	0h	Refer "CH1_DW_SEL" field description
6	CH1_BYTE_SWAP	R/W	0h	BYTE SWAP Enable across Data Size 0 Byte Swap Disabled 1 Byte Swap enabled.
5	CH1_BIT_SWAP	R/W	0h	msb/lsb SWAPPING 0 msb [most significant bit First] 1 lsb [least significant bit First]
4:3	CH1_CRC_SEL	R/W	0h	CRC type select. {CH1_CRC_SEL2,CH1_CRC_SEL[1:0]} 000 CRC-64 001 - CRC-16 010 CRC-32 100 - VDA CAN, SAE-J1850 CRC-8 101 - H2F, Autosar 4.0 110 - CASTAGNOLI, iSCSI 111 / 011 - E2E Profile 4
2:1	CH1_DW_SEL	R/W	0h	CRC Data Size select. 000 64 bit Data Size 001 - 16 bit Data Size 010 32 Bit Data Size
0	CH1_PSA_SWREST	R/W	0h	Channel 1 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore, CPU is required to clear this bit by Writing a 0. 0 = PSA Signature Register not reset 1 = PSA Signature Register reset