SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
INTR Interrupt Enable/Clear Register.
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| Instance Name | Physical Address |
|---|---|
| QSPI0 | 4820 002Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | WIRQ_ENA_CLR | FIRQ_ENA_CLR | |||||
| R | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:2 | RESERVED | R | 0h | Always read as 0 |
| 1 | WIRQ_ENA_CLR | R/W | 0h | Word Interrupt Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect |
| 0 | FIRQ_ENA_CLR | R/W | 0h | Frame Interrupt Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect |