SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
SPI Data Control Register (SPIDC).
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| Instance Name | Physical Address |
|---|---|
| QSPI0 | 4820 0044h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED4 | DD3 | CKPH3 | CSP3 | CKP3 | |||
| R | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED3 | DD2 | CKPH2 | CSP2 | CKP2 | |||
| R | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED2 | DD1 | CKPH1 | CSP1 | CKP1 | |||
| R | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED1 | DD0 | CKPH0 | CSP0 | CKP0 | |||
| R | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:29 | RESERVED4 | R | 0h | Always read as 0 |
| 28:27 | DD3 | R/W | 0h | Data delay for chip select 3 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active |
| 26 | CKPH3 | R/W | 0h | Clock phase for chip select 3 If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge |
| 25 | CSP3 | R/W | 0h | Chip select polarity for chip select 3 0- Active low 1- Active high |
| 24 | CKP3 | R/W | 0h | Clock polarity for chip select 3 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1 |
| 23:21 | RESERVED3 | R | 0h | Always read as 0 |
| 20:19 | DD2 | R/W | 0h | Data delay for chip select 2 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active |
| 18 | CKPH2 | R/W | 0h | Clock phase for chip select 2. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge |
| 17 | CSP2 | R/W | 0h | Chip select polarity for chip select 2 0- Active low 1- Active high |
| 16 | CKP2 | R/W | 0h | Clock polarity for chip select 2 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1 |
| 15:13 | RESERVED2 | R | 0h | Always read as 0 |
| 12:11 | DD1 | R/W | 0h | Data delay for chip select 1 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active |
| 10 | CKPH1 | R/W | 0h | Clock phase for chip select 1. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge |
| 9 | CSP1 | R/W | 0h | Chip select polarity for chip select 1 0- Active low 1- Active high |
| 8 | CKP1 | R/W | 0h | Clock polarity for chip select 1 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1 |
| 7:5 | RESERVED1 | R | 0h | Always read as 0 |
| 4:3 | DD0 | R/W | 0h | Data delay for chip select 0 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active |
| 2 | CKPH0 | R/W | 0h | Clock phase for chip select 0. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge |
| 1 | CSP0 | R/W | 0h | Chip select polarity for chip select 0 0- Active low 1- Active high |
| 0 | CKP0 | R/W | 0h | Clock polarity for chip select 0 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1 |