SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

21.2.18.1 QSPI_SPI_CMD Register (Offset = 48h) [reset = 0h]

SPI Command Register (SPICR).

Table 5-2158 Instance Table

Instance Name	Physical Address
QSPI0	4820 0048h

Figure 5-1062 QSPI_SPI_CMD Name Register

Table 5-2159 QSPI_SPI_CMD Register Field Descriptions

Bit	Field	Type	Reset	Description
31:30	RESERVED3	R	0h	Always read as 0
29:28	CSNUM	R/W	0h	Device select. Sets the active chip select for the transfer 00- Chip Select 0 active 01- Chip Select 1 active 10- Chip Select 2 active 11- Chip Select 3 active
27:26	RESERVED2	R	0h	Always read as 0
25:19	WLEN	R/W	0h	Word length. Sets the size of the individual transfers from 1 128 bits 0- 1 bit 1- 2 bits 127 128 bits
18:16	CMD	R/W	0h	Transfer command 000- Reserved 001- 4 pin Read Single 010- 4 pin Write Single 011- 4 pin Read Dual 100 Reserved 101 3 pin Read Single 110 3 pin Write Single 111 6 pin Read Quad
15	FIRQ	R/W	0h	Frame count interrupt enable
14	WIRQ	R/W	0h	Word count interrupt enable
13:12	RESERVED1	R	0h	Always read as 0
11:0	FLEN	R/W	0h	Frame Length 0- 1 word 1- 2 words 4095 4096words