SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

1.2.83.1 ECC_AGG_CORE1_CONTROL Register (Offset = 14h) [reset = 187h]

ECC Control Register.

Table 4-184 Instance Table

Instance Name	Physical Address
R5SS0	5300 3014h
R5SS1	5300 7014h

Figure 4-83 ECC_AGG_CORE1_CONTROL Name Register

Table 4-185 ECC_AGG_CORE1_CONTROL Register Field Descriptions

Bit	Field	Type	Reset	Description
31:9	RESERVED	NONE	0h	Reserved
8	CHECK_SVBUS_TIMEOUT	R/W	1h	check for svbus timeout errors
7	CHECK_PARITY	R/W	1h	check for parity errors
6	ERROR_ONCE	R/W	0h	Force Error only once
5	FORCE_N_ROW	R/W	0h	Force Error on any RAM read
4	FORCE_DED	R/W	0h	Force Double Bit Error
3	FORCE_SEC	R/W	0h	Force Single Bit Error
2	ENABLE_RMW	R/W	1h	Enable rmw
1	ECC_CHECK	R/W	1h	Enable ECC check
0	ECC_ENABLE	R/W	1h	Enable ECC