SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

1.2.134.1 CPSW_NC_ETH_MAC_PN_FIFO_STATUS_REG_K Register (Offset = 22050h) [reset = FF00h]

Enet Port N FIFO STATUS

Offset = Base + (k * 1000h); where k = 0 to 1d

Table 5-268 Instance Table

Instance Name	Physical Address
CPSW0	5282 2050h + formula

Figure 5-134 CPSW_NC_ETH_MAC_PN_FIFO_STATUS_REG_K Name Register

Table 5-269 CPSW_NC_ETH_MAC_PN_FIFO_STATUS_REG_K Register Field Descriptions

Bit	Field	Type	Reset	Description
31:19	RESERVED	NONE	0h	Reserved
18	EST_BUFACT	R	0h	EST RAM active buffer - Indicates the active 64-word fetch buffer when pn_est_onebuf is cleared to zero. Indicates the fetch ram address MSB when pn_est_onebuf set to one.
17	EST_ADD_ERR	R	0h	EST Address Error - Indicates that the fetch ram was read again after the previous maximum buffer address read (the previous fetch from the maximum address is reused).
16	EST_CNT_ERR	R	0h	EST Fetch Count Error - Indicates that insufficient clocks were programmed into the fetch count and that another fetch was commanded before the previous fetch finished.
15:8	TX_E_MAC_ALLOW	R	FFh	Transmit mac allow - Bus that indicates the actual priorities assigned to the express queue (and inversely the priorities assigned to the prempt queue). The pn_mac_prempt[7:0] field in the Enet_Pn_IET_Control register indicates which priorities should be assigned to the express/prempt queues. The switch between queues happens only when the priority is empty and the actual assignment is shown in this field.
7:0	TX_PRI_ACTIVE	R	0h	Transmit Priority Active - Bus that indicates which priorities have packets (non-empty) at the time of the register read.