SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

9.2.4.1 GPMC_IRQENABLE Register (Offset = 1Ch) [reset = 0h]

The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis.

Table 5-1174 Instance Table

Instance Name	Physical Address
GPMC0	4840 001Ch

Figure 5-582 GPMC_IRQENABLE Name Register

Table 5-1175 GPMC_IRQENABLE Register Field Descriptions

Bit	Field	Type	Reset	Description
31:12	RESERVED_216	R	0h	Write 0's for future compatibility. Read returns 0
11	WAIT3EDGEDETECTIONENABLE	R/W	0h	Enables the Wait3 Edge Detection interrupt 1 Wait3EdgeDetection event generates an interrupt if occurs 0 Wait3EdgeDetection interrupt is masked
10	WAIT2EDGEDETECTIONENABLE	R/W	0h	Enables the Wait2 Edge Detection interrupt 1 Wait2EdgeDetection event generates an interrupt if occurs 0 Wait2EdgeDetection interrupt is masked
9	WAIT1EDGEDETECTIONENABLE	R/W	0h	Enables the Wait1 Edge Detection interrupt 1 Wait1EdgeDetection event generates an interrupt if occurs 0 Wait1EdgeDetection interrupt is masked
8	WAIT0EDGEDETECTIONENABLE	R/W	0h	Enables the Wait0 Edge Detection interrupt 1 Wait0EdgeDetection event generates an interrupt if occurs 0 Wait0EdgeDetection interrupt is masked
7:2	RESERVED_217	R	0h	Write 0's for future compatibility. Read returns 0
1	TERMINALCOUNTEVENTENABLE	R/W	0h	Enables TerminalCountEvent interrupt issuing in pre-fetch or write posting mode 1 TerminalCountEvent interrupt is not masked 0 TerminalCountEvent interrupt is masked
0	FIFOEVENTENABLE	R/W	0h	Enables the FIFOEvent interrupt 1 FIFOEvent interrupt is not masked 0 FIFOEvent interrupt is masked