SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
The GPMC_TIMEOUT_CONTROL register allows the user to set the start value of the timeout counter
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| Instance Name | Physical Address |
|---|---|
| GPMC0 | 4840 0040h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_237 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_237 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_237 | TIMEOUTSTARTVALUE | ||||||
| R | R/W | ||||||
| 0h | 1FFh | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TIMEOUTSTARTVALUE | RESERVED_238 | TIMEOUTENABLE | |||||
| R/W | R | R/W | |||||
| 1FFh | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:13 | RESERVED_237 | R | 0h | Write 0's for future compatibility. Read returns 0 |
| 12:4 | TIMEOUTSTARTVALUE | R/W | 1FFh | Start value of the time-out counter [0x000 corresponds to 0 GPMC.FCLK cycle, 0x001 corresponds to 1 GmpcClk cycle, &, 0x1FF corresponds to 511 GPMC.FCLK cyles.] |
| 3:1 | RESERVED_238 | R | 0h | Write 0's for future compatibility. Read returns 0 |
| 0 | TIMEOUTENABLE | R/W | 0h | Enable bit of the TimeOut feature 1 TimeOut feature is enabled 0 TimeOut feature is disabled |