SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

9.2.9.1 GPMC_STATUS Register (Offset = 54h) [reset = 1h]

The status register provides global status bits of the GPMC .

Table 5-1184 Instance Table

Instance Name	Physical Address
GPMC0	4840 0054h

Figure 5-587 GPMC_STATUS Name Register

Table 5-1185 GPMC_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
31:12	RESERVED_231	R	0h	Write 0's for future compatibility. Read returns 0
11	WAIT3STATUS	R	0h	Is a copy of input pin WAIT3. [Reset value is WAIT3 input pin sampled at IC reset] 1 WAIT3 asserted 0 WAIT3 de-asserted
10	WAIT2STATUS	R	0h	Is a copy of input pin WAIT2. [Reset value is WAIT2 input pin sampled at IC reset] 1 WAIT2 asserted 0 WAIT2 de-asserted
9	WAIT1STATUS	R	0h	Is a copy of input pin WAIT1. [Reset value is WAIT1 input pin sampled at IC reset] 1 WAIT1 asserted 0 WAIT1 de-asserted
8	WAIT0STATUS	R	0h	Is a copy of input pin WAIT0. [Reset value is WAIT0 input pin sampled at IC reset] 1 WAIT0 asserted 0 WAIT0 de-asserted
7:1	RESERVED_232	R	0h	Write 0's for future compatibility Reads returns 0
0	EMPTYWRITEBUFFERSTATUS	R	1h	Stores the empty status of the write buffer 1 Write Buffer is empty 0 Write Buffer is not empty