SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

9.2.15.1 GPMC_ECC_CONTROL Register (Offset = 1F8h) [reset = 0h]

ECC control .

Table 5-1196 Instance Table

Instance Name	Physical Address
GPMC0	4840 01F8h

Figure 5-593 GPMC_ECC_CONTROL Name Register

Table 5-1197 GPMC_ECC_CONTROL Register Field Descriptions

Bit	Field	Type	Reset	Description
31:9	RESERVED_207	R	0h	Write 0's for future compatibility. Read returns 0
8	ECCCLEAR	R/W1TC	0h	Clear all ECC result registers [Reads returns 0 - Writes 1 to this field clear all ECC result registers - Writes 0 are ignored]
7:4	RESERVED_208	R	0h	Write 0's for future compatibility. Read returns 0
3:0	ECCPOINTER	R/W	0h	Selects ECC result register [Reads to this field give the dynamic position of the ECC pointer - Writes to this field select the ECC result register where the first ECC computation will be stored]; Other enums: Writing other values disables the ECC engine [ECCEnable bit of GPMC_ECC_CONFIG set to 0] 9 ECC result register 9 is selected 8 ECC result register 8 is selected 7 ECC result register 7 is selected 6 ECC result register 6 is selected 5 ECC result register 5 is selected 4 ECC result register 4 is selected 3 ECC result register 3 is selected 2 ECC result register 2 is selected 1 ECC result register 1 is selected 0 writing 0000 disables the ECC engine (ECCEnable bit of GPMC_ECC_CONFIG set to 0)