SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

9.2.17.1 GPMC_ECC_RESULT_J Register (Offset = 200h) [reset = 0h]

ECC result register .

Offset = Base + (j * 4h); where j = 0 to 8d

Table 5-1200 Instance Table

Instance Name	Physical Address
GPMC0	4840 0200h + formula

Figure 5-595 GPMC_ECC_RESULT_J Name Register

Table 5-1201 GPMC_ECC_RESULT_J Register Field Descriptions

Bit	Field	Type	Reset	Description
31:28	RESERVED_188	R	0h	Write 0's for future compatibility. Read returns 0
27	P2048O	R	0h	Odd Row Parity bit 2048 only used for ECC computed on 512 Bytes
26	P1024O	R	0h	Odd Row Parity bit 1024
25	P512O	R	0h	Odd Row Parity bit 512
24	P256O	R	0h	Odd Row Parity bit 256
23	P128O	R	0h	Odd Row Parity bit 128
22	P64O	R	0h	Odd Row Parity bit 64
21	P32O	R	0h	Odd Row Parity bit 32
20	P16O	R	0h	Odd Row Parity bit 16
19	P8O	R	0h	Odd Row Parity bit 8
18	P4O	R	0h	Odd Column Parity bit 4
17	P2O	R	0h	Odd Column Parity bit 2
16	P1O	R	0h	Odd Column Parity bit 1
15:12	RESERVED_187	R	0h	Write 0's for future compatibility. Read returns 0
11	P2048E	R	0h	Even Row Parity bit 2048 only used for ECC computed on 512 Bytes
10	P1024E	R	0h	Even Row Parity bit 1024
9	P512E	R	0h	Even Row Parity bit 512
8	P256E	R	0h	Even Row Parity bit 256
7	P128E	R	0h	Even Row Parity bit 128
6	P64E	R	0h	Even Row Parity bit 64
5	P32E	R	0h	Even Row Parity bit 32
4	P16E	R	0h	Even Row Parity bit 16
3	P8E	R	0h	Even Row Parity bit 8
2	P4E	R	0h	Even Column Parity bit 4
1	P2E	R	0h	Even Column Parity bit 2
0	P1E	R	0h	Even Column Parity bit 1