SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.9.2.19 GPMC_CONFIG1 Register

9.2.19.1 GPMC_CONFIG1 Register (Offset = 60h) [reset = 0h]

The configuration 1 register sets signal control parameters per chip select

Offset = Base + (j * 30h); where j = 0 to 3d

Table 5-1204 Instance Table

Instance Name	Physical Address
GPMC0	4840 0060h + formula

Figure 5-597 GPMC_CONFIG1 Name Register

31	30	29	28	27	26	25	24
WRAPBURST	READMULTIPLE	READTYPE	WRITEMULTIPLE	WRITETYPE	CLKACTIVATIONTIME		ATTACHEDDEVICEPAGELENGTH
R/W	R/W	R/W	R/W	R/W	R/W		R/W
0h	0h	0h	0h	0h	0h		0h
23	22	21	20	19	18	17	16
ATTACHEDDEVICEPAGELENGTH	WAITREADMONITORING	WAITWRITEMONITORING	RESERVED_9	WAITMONITORINGTIME		WAITPINSELECT
R/W	R/W	R/W	R	R/W		R/W
0h	0h	0h	0h	0h		0h
15	14	13	12	11	10	9	8
RESERVED_11		DEVICESIZE		DEVICETYPE		MUXADDDATA
R		R/W		R/W		R/W
0h		0h		0h		0h
7	6	5	4	3	2	1	0
RESERVED_12			TIMEPARAGRANULARITY	RESERVED_10		GPMCFCLKDIVIDER
R			R/W	R		R/W
0h			0h	0h		0h

Table 5-1205 GPMC_CONFIG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	WRAPBURST	R/W	0h	Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst 1 Synchronous wrapping burst supported 0 Synchronous wrapping burst not supported
30	READMULTIPLE	R/W	0h	Selects the read single or multiple access 1 multiple access (burst if synchonous, page if asynchronous) 0 single access
29	READTYPE	R/W	0h	Selects the read mode operation 1 Read Synchronous 0 Read Asynchronous
28	WRITEMULTIPLE	R/W	0h	Selects the write single or multiple access 1 multiple access (burst if synchonous, considered as single if asynchronous) 0 single access
27	WRITETYPE	R/W	0h	Selects the write mode operation 1 Write Synchronous 0 Write Asynchronous
26:25	CLKACTIVATIONTIME	R/W	0h	Output GPMC.CLK activation time 3 not defined 2 First rising edge of GPMC.CLK two GPMC.FCLK cycles after Start Access Time 1 First rising edge of GPMC.CLK one GPMC.FCLK cycle after Start Access Time 0 First rising edge of GPMC.CLK at Start Access Time
24:23	ATTACHEDDEVICEPAGELENGTH	R/W	0h	Specifies the attached device page [burst] length 3 32 Words 2 16 Words 1 8 Words 0 4 Words
22	WAITREADMONITORING	R/W	0h	Selects the Wait monitoring configuration for Read accesses [Reset value is BOOTWAITEN input pin sampled at IC reset] 1 Wait pin is monitored for read accesses 0 Wait pin is not monitored for read accesses
21	WAITWRITEMONITORING	R/W	0h	Selects the Wait monitoring configuration for Write accesses 1 Wait pin is monitored for write accesses 0 Wait pin is not monitored for write accesses
20	RESERVED_9	R	0h	Write 0's for future compatibility. Read returns 0
19:18	WAITMONITORINGTIME	R/W	0h	Selects input pin Wait monitoring time 3 not defined 2 Wait pin is monitored two GPMC.CLK cycle before valid data 1 Wait pin is monitored one GPMC.CLK cycle before valid data 0 Wait pin is monitored with valid data
17:16	WAITPINSELECT	R/W	0h	Selects the input WAIT pin for this chip select [Reset value is BOOTWAITSELECT input pin sampled at IC reset for CS0 and 0 for CS1-7] 3 Wait input pin is WAIT3 2 Wait input pin is WAIT2 1 Wait input pin is WAIT1 0 Wait input pin is WAIT0
15:14	RESERVED_11	R	0h	Write 0's for future compatibility. Read returns 0
13:12	DEVICESIZE	R/W	0h	Selects the device size attached [Reset value is BOOTDEVICESIZE input pin sampled at IC reset for CS0 and 01 for CS1-7] 3 reserved 2 32 bit 1 16 bit 0 8 bit
11:10	DEVICETYPE	R/W	0h	Selects the attached device type 3 reserved 2 NAND Flash stream mode 1 reserved 0 NOR Flash, pSRAM, asynchronous devices
9:8	MUXADDDATA	R/W	0h	Enables the Address and data multiplexed protocol [Reset value is CS0MUXDEVICE input pin sampled at IC reset for CS0 and 0 for CS1-7] 3 Reserved 2 Address and data multiplexed attached device 1 AAD-Mux protocol device 0 Non Multiplexed attached device
7:5	RESERVED_12	R	0h	Write 0's for future compatibility. Read returns 0
4	TIMEPARAGRANULARITY	R/W	0h	Signals timing latencies scalar factor [Rd/WRCycleTime, AccessTime, PageBurstAccessTime, CSOnTime, CSRd/WrOffTime, ADVOnTime, ADVRd/WrOffTime, OEOnTime, OEOffTime, WEOnTime, WEOffTime, Cycle2CycleDelay, BusTurnAround, TimeOutStartValue] 1 x2 latencies 0 x1 latencies
3:2	RESERVED_10	R	0h	Write 0's for future compatibility. Read returns 0
1:0	GPMCFCLKDIVIDER	R/W	0h	Divides the GPMC.FCLK clock 3 GPMC.CLK frequency = GPMC.FCLK frequency /4 2 GPMC.CLK frequency = GPMC.FCLK frequency / 3 1 GPMC.CLK frequency = GPMC.FCLK frequency / 2 0 GPMC.CLK frequency = GPMC.FCLK frequency