SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

9.2.20.1 GPMC_CONFIG2 Register (Offset = 64h) [reset = 101001h]

Chip-select signal timing parameter configuration

Offset = Base + (j * 30h); where j = 0 to 3d

Table 5-1206 Instance Table

Instance Name	Physical Address
GPMC0	4840 0064h + formula

Figure 5-598 GPMC_CONFIG2 Name Register

Table 5-1207 GPMC_CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31:21	RESERVED_43	R	0h	Write 0's for future compatibility Reads returns 0
20:16	CSWROFFTIME	R/W	10h	CS# de-assertion time from start cycle time for write accesses [0x00 corresponds to 0 GPMC.FCLK cycle, 0x01 corresponds to 1 GPMC.FCLK cycle, &, 0x1F corresponds to 31 GPMC.FCLK cycles]
15:13	RESERVED_45	R	0h	Write 0's for future compatibility. Read returns 0
12:8	CSRDOFFTIME	R/W	10h	CS# de-assertion time from start cycle time for read accesses [0x00 corresponds to 0 GPMC.FCLK cycle, 0x01 corresponds to 1 GPMC.FCLK cycle, &, 0x1F corresponds to 31 GPMC.FCLK cycles]
7	CSEXTRADELAY	R/W	0h	CS# Add Extra Half GPMC.FCLK cycle 1 CS# Timing control signal is delayed of half GPMC.FCLK clock cycle 0 CS# Timing control signal is not delayed
6:4	RESERVED_44	R	0h	Write 0's for future compatibility. Read returns 0
3:0	CSONTIME	R/W	1h	CS# assertion time from start cycle time [0x0 corresponds to 0 GPMC.FCLK cycle, 0x1 corresponds to 1 GPMC.FCLK cycle, &, 0xF corresponds to 15 GPMC.FCLK cycles]